公开(公告)号：US11923373B2

公开(公告)日：2024-03-05

申请号：US17502026

申请日：2021-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo Tao ,  Li Wang ,  Ching-Yang Wen ,  Purakh Raj Verma ,  Zhibiao Zhou ,  Dong Yin ,  Gang Ren ,  Jian Xie

IPC: H01L27/12 ,  G11C17/16 ,  H01L23/525 ,  H10B20/20 ,  H10B20/25

CPC classification number: H01L27/1207 ,  G11C17/16 ,  G11C17/165 ,  H01L23/5252 ,  H10B20/20 ,  H10B20/25

Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.

公开(公告)号：US10103273B2

公开(公告)日：2018-10-16

申请号：US15447081

申请日：2017-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/24 ,  H01L29/04 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06

Abstract: A semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure.

公开(公告)号：US10037914B2

公开(公告)日：2018-07-31

申请号：US15655920

申请日：2017-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Xing Hua Zhang

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L21/76895 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L23/485 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/456 ,  H01L29/66568 ,  H01L29/66659 ,  H01L29/7831

Abstract: A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate, the spacer and the doping region, and a redistributed contact layer (RCL) on the insulating cap layer. The RCL extends from the active area to the trench isolation region. A contact plug is disposed above the trench isolation region and is electrically connected to the gate or the doping region through the RCL.

公开(公告)号：US09966428B2

公开(公告)日：2018-05-08

申请号：US14996244

申请日：2016-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L49/02

CPC classification number: H01L28/91

Abstract: A method for fabricating capacitor is disclosed. The method includes the steps of: providing a material layer; forming a first conductive layer, a first dielectric layer, and a second conductive layer on the material layer; patterning the first dielectric layer and the second conductive layer to form a patterned first dielectric layer and a middle electrode; forming a second dielectric layer on the first conductive layer and the middle electrode; removing part of the second dielectric layer to form a patterned second dielectric layer; forming a third conductive layer on the first conductive layer and the patterned second dielectric layer, wherein the third conductive layer contacts the first conductive layer directly; and removing part of the third conductive layer to expose part of the patterned second dielectric layer.

公开(公告)号：US09455351B1

公开(公告)日：2016-09-27

申请号：US14841731

申请日：2015-09-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Chun-Yuan Wu

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/66969

Abstract: An oxide semiconductor field effect transistor (OS FET) device includes a first dielectric layer formed on a substrate, an oxide semiconductor (OS) island formed on the first dielectric layer, a first gate electrode formed on the OS island, a gate dielectric layer formed in between the first gate electrode and the OS island, a patterned hard mask layer formed on a top surface of the first gate electrode, an etch stop layer covering a top surface of the patterned hard mask layer and sidewalls of the first gate electrode, and a source electrode and a drain electrode formed on the OS island. At least one of the source electrode and the drain electrode partially overlaps the etching stop layer on the sidewalls of the first gate electrode.

Abstract translation: 一种氧化物半导体场效应晶体管（OS FET）器件包括形成在基板上的第一介电层，形成在第一介电层上的氧化物半导体（OS）岛，形成在OS岛上的第一栅电极，形成的栅介质层 在第一栅电极和OS岛之间，形成在第一栅电极的顶表面上的图案化硬掩模层，覆盖图案化硬掩模层的顶表面和第一栅电极的侧壁的蚀刻停止层，以及 形成在OS岛上的源电极和漏电极。 源极电极和漏极电极中的至少一个部分地与第一栅电极的侧壁上的蚀刻停止层重叠。

公开(公告)号：US09064719B1

公开(公告)日：2015-06-23

申请号：US14324090

申请日：2014-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L23/52 ,  H01L27/06 ,  H01L27/12

CPC classification number: H01L27/0688 ,  H01L27/0629 ,  H01L27/0682 ,  H01L27/1203 ,  H01L2224/48247

Abstract: An integrated circuit includes a capacitor and a non-inductive resistor. A substrate has a capacitor area and a resistor area. A patterned stacked structure including a bottom conductive layer, an insulating layer and a top conductive layer from bottom to top is sandwiched by a first dielectric layer and a second dielectric layer disposed on the substrate. A first metal plug and a second metal plug contact the top conductive layer and the bottom conductive layer of the capacitor area respectively, thereby the patterned stacked structure in the capacitor area constituting the capacitor. A third metal plug and a fourth metal plug contact the bottom conductive layer and the top conductive layer of the resistor area respectively, and a fifth metal plug contacts the bottom conductive layer and the top conductive layer of the resistor area simultaneously, thereby the patterned stacked structure in the resistor area constituting the non-inductive resistor.

Abstract translation: 集成电路包括电容器和非感性电阻器。 衬底具有电容器区域和电阻器区域。 包括底部导电层，绝缘层和从顶部到顶部的顶部导电层的图案化堆叠结构被设置在基板上的第一介电层和第二介电层夹在中间。 第一金属插塞和第二金属插头分别与电容器区域的顶部导电层和底部导电层接触，从而构成电容器区域中的图案化堆叠结构。 第三金属插塞和第四金属插头分别接触电阻器区域的底部导电层和顶部导电层，并且第五金属插头同时接触电阻器区域的底部导电层和顶部导电层，由此图案化堆叠 构成无感电阻器的电阻区域的结构。

公开(公告)号：US11561403B2

公开(公告)日：2023-01-24

申请号：US17355196

申请日：2021-06-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou

IPC: G02B27/01 ,  H01L25/075 ,  H01L33/62

Abstract: A layout of Micro LED for augmented reality (AR) and mixed reality (MR) is provided in the present invention, including multiple display cells arranging into a cell array, multiple micro LEDs set on the edge region of each display cell and exposing the transparent region surrounded by the edge region, and pixel driver circuits set on the edge region right under the Micro LEDs.

公开(公告)号：US10102907B2

公开(公告)日：2018-10-16

申请号：US15382755

申请日：2016-12-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Chen-Bin Lin ,  Chi-Fa Ku ,  Shao-Hui Wu

IPC: H01L27/108 ,  H01L29/786 ,  G11C14/00 ,  H01L49/02 ,  H01L27/12 ,  H01L21/02

Abstract: A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared. At least a first dielectric layer is formed on the main surface of the semiconductor substrate. A first OS FET device and a second OS FET device are formed on the first dielectric layer. At least a second dielectric layer is formed to cover the first dielectric layer, the first OS FET device, and the second OS FET device. A first MIM capacitor and a second MIM capacitor are formed on the second dielectric layer. The first MIM capacitor is electrically coupled to the first OS FET device, thereby constituting a DOSRAM cell. The second MIM capacitor is electrically coupled to the second OS FET device, thereby constituting a NOSRAM cell.

公开(公告)号：US09991266B2

公开(公告)日：2018-06-05

申请号：US15180095

申请日：2016-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen

IPC: H01L27/108 ,  H01L29/423 ,  H01L27/12 ,  H01L29/786 ,  H01L49/02 ,  H01L23/528

CPC classification number: H01L27/10814 ,  H01L23/528 ,  H01L27/10897 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/42356 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor array, the semiconductor memory array includes bit lines, word lines and memory cells. The bit lines are arranged in parallel in a first direction, and the word lines are arranged in parallel in a second direction which is different from the first direction. The memory cells are arranged in an array and electrically connected to corresponding bit lines and word lines respectively, and any two memory cells adjacent to each other share a same oxide semiconductor layer as a channel layer. The present invention also relates to a semiconductor memory device including two memory cells sharing a same oxide semiconductor layer as a channel layer.

公开(公告)号：US09899365B1

公开(公告)日：2018-02-20

申请号：US15409498

申请日：2017-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen

IPC: H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L27/0207 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/092 ,  H01L27/11807 ,  H01L2027/11875

Abstract: A layout of a semiconductor device includes a first active area, a second active area, plural gates, a first conductive layout and plural plugs. The first and the second active areas are disposed on a substrate and surrounded by a shallow trench isolation (STI). The plural gates are parallel with one another and cross the first and the second active areas. The first conductive layer covers the plural gates, and the plural gates are electrically connected to each other through the first conductive layer. The plural plugs are disposed on the first conductive layer to electrically connect the plural gates.