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公开(公告)号：US11087812B1
公开(公告)日：2021-08-10
申请号：US16931438
申请日：2020-07-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yi-Hui Lee , I-Ming Tseng , Chiu-Jung Chiu , Chung-Liang Chu , Yu-Chun Chen , Ya-Sheng Feng , Yi-An Shih , Hsiu-Hao Hu , Yu-Ping Wang
Abstract: A MRAM includes a plurality of memory cells, an operation unit, a voltage generator, and an input/output circuit. The operation unit includes multiple groups of memory cells among the plurality of memory cells. The voltage generator is configured to provide a plurality of control signals by voltage-dividing a voltage control signal and selectively output the plurality of control signals to the input/output circuit. The input/output circuit is configured to output a plurality of switching pulse signals to the multiple groups of memory cells according to the plurality of control signals, wherein each switching pulse signal differs in pulse width or level.
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公开(公告)号：US20240357943A1
公开(公告)日：2024-10-24
申请号：US18760005
申请日：2024-06-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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公开(公告)号：US20220029087A1
公开(公告)日：2022-01-27
申请号：US16997922
申请日：2020-08-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Chun Chen , Yen-Chun Liu , Ya-Sheng Feng , Chiu-Jung Chiu , I-Ming Tseng , Yi-An Shih , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A semiconductor device includes a substrate having a magnetic random access memory (MRAM) region and a logic region, a first metal interconnection on the MRAM region, a second metal interconnection on the logic region, a stop layer extending from the first metal interconnection to the second metal interconnection, and a magnetic tunneling junction (MTJ) on the first metal interconnection. Preferably, the stop layer on the first metal interconnection and the stop layer on the second metal interconnection have different thicknesses.
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公开(公告)号：US20240365677A1
公开(公告)日：2024-10-31
申请号：US18329588
申请日：2023-06-06
Applicant: United Microelectronics Corp.
Inventor： Jia-Rong Wu , Yi-An Shih , Hsiu-Hao Hu , I-Fan Chang , Rai-Min Huang , Po Kai Hsu
Abstract: Provided is a semiconductor device including a substrate, a first interconnection structure, and an MTJ device. The first interconnection structure is disposed on the substrate. The MTJ device is reversely bonded to the first interconnection structure. The MTJ device includes a first electrode layer, a second electrode layer and an MTJ stack structure. The first electrode layer is bonded to the first interconnect structure. The second electrode layer is located above the first electrode layer. The MTJ stack structure is located between the first and second electrode layers. The MTJ stack structure includes a first barrier layer, a free layer and a reference layer. The first barrier layer is located between the first and second electrode layers. The free layer is located between the first barrier layer and the first electrode layer. The reference layer is located between the first barrier layer and the second electrode layer.
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公开(公告)号：US11476410B2
公开(公告)日：2022-10-18
申请号：US16997922
申请日：2020-08-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Chun Chen , Yen-Chun Liu , Ya-Sheng Feng , Chiu-Jung Chiu , I-Ming Tseng , Yi-An Shih , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A semiconductor device includes a substrate having a magnetic random access memory (MRAM) region and a logic region, a first metal interconnection on the MRAM region, a second metal interconnection on the logic region, a stop layer extending from the first metal interconnection to the second metal interconnection, and a magnetic tunneling junction (MTJ) on the first metal interconnection. Preferably, the stop layer on the first metal interconnection and the stop layer on the second metal interconnection have different thicknesses.
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Patent Agency Ranking
公开(公告)号：US20220013713A1
公开(公告)日：2022-01-13
申请号：US16988707
申请日：2020-08-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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公开(公告)号：US12063871B2
公开(公告)日：2024-08-13
申请号：US18230189
申请日：2023-08-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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公开(公告)号：US20230380296A1
公开(公告)日：2023-11-23
申请号：US18230189
申请日：2023-08-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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公开(公告)号：US11765983B2
公开(公告)日：2023-09-19
申请号：US17972542
申请日：2022-10-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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公开(公告)号：US20230040932A1
公开(公告)日：2023-02-09
申请号：US17972542
申请日：2022-10-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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