公开(公告)号：US20240379492A1

公开(公告)日：2024-11-14

申请号：US18780438

申请日：2024-07-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/00 ,  H01L23/373 ,  H01L23/48 ,  H01L23/485 ,  H01L25/00 ,  H01L25/07

Abstract: A semiconductor structure with a heat dissipation structure includes a first device wafer includes a front side and a back side. A first transistor is disposed on the front side. The first transistor includes a first gate structure disposed on the front side. Two first source/drain doping regions are embedded within the first device wafer at two side of the first gate structure. A channel region is disposed between the two first source/drain doping regions and embedded within the first device wafer. A first dummy metal structure contacts the back side of the first device wafer, and overlaps the channel region.

公开(公告)号：US20240234350A9

公开(公告)日：2024-07-11

申请号：US17989633

申请日：2022-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Ching-Yang Wen ,  XINGXING CHEN

IPC: H01L23/00 ,  H01L25/16 ,  H01L27/12 ,  H01L49/02

CPC classification number: H01L24/08 ,  H01L24/16 ,  H01L25/16 ,  H01L27/1203 ,  H01L28/90 ,  H01L2224/08145 ,  H01L2224/16227

Abstract: A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.

公开(公告)号：US11923373B2

公开(公告)日：2024-03-05

申请号：US17502026

申请日：2021-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo Tao ,  Li Wang ,  Ching-Yang Wen ,  Purakh Raj Verma ,  Zhibiao Zhou ,  Dong Yin ,  Gang Ren ,  Jian Xie

IPC: H01L27/12 ,  G11C17/16 ,  H01L23/525 ,  H10B20/20 ,  H10B20/25

CPC classification number: H01L27/1207 ,  G11C17/16 ,  G11C17/165 ,  H01L23/5252 ,  H10B20/20 ,  H10B20/25

Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.

公开(公告)号：US11881529B2

公开(公告)日：2024-01-23

申请号：US17902928

申请日：2022-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Ching-Yang Wen ,  Li Wang ,  Kai Cheng

IPC: H01L23/52 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/7838 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66484 ,  H01L29/7831

Abstract: A method of fabricating a semiconductor device is provided. First, a semiconductor structure is provided, and the semiconductor structure includes a buried dielectric layer, a first gate structure disposed on a front-side of the buried dielectric layer, and a first source/drain region and a second source/drain region disposed between the buried dielectric layer and the first gate structure. Then, a trench is formed in the buried dielectric layer. Afterwards, a conductive layer is formed on the buried dielectric layer and in the trench. Finally, the conductive layer is patterned.

公开(公告)号：US20230268246A1

公开(公告)日：2023-08-24

申请号：US18136329

申请日：2023-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Liang Liao ,  Purakh Raj Verma ,  Ching-Yang Wen ,  Chee Hau Ng

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/3735 ,  H01L21/4871 ,  H01L23/15 ,  H01L23/3736

Abstract: A semiconductor structure includes a glass substrate and a device structure. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.

公开(公告)号：US11721757B2

公开(公告)日：2023-08-08

申请号：US17391048

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/266 ,  H01L21/285 ,  H01L29/78

CPC classification number: H01L29/7824 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/78624 ,  H01L21/266 ,  H01L21/28518 ,  H01L29/665

Abstract: A LDMOS device includes a semiconductor layer on an insulation layer and a ring shape gate on the semiconductor layer. The ring shape gate includes a first gate portion, a second gate portion, and two third gate portions connecting the first gate portion and the second gate portion. The semiconductor device further includes a first drain region and a second drain region formed in the semiconductor layer at two sides of the ring shape gate, a plurality of source regions formed in the semiconductor layer surrounded by the ring shape gate, a plurality of body contact regions formed in the semiconductor layer and arranged between the source regions, and a first body implant region and a second body implant region formed in the semiconductor layer, respectively underlying part of the first gate portion and part of the second gate portion, and being connected by the body contact regions.

公开(公告)号：US11715709B2

公开(公告)日：2023-08-01

申请号：US17715067

申请日：2022-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Wen-Shen Li ,  Ching-Yang Wen

IPC: H01L23/66 ,  H01L23/48 ,  H01L23/52 ,  H01L21/762 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/66 ,  H01L21/565 ,  H01L21/76243 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5226 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/6616

Abstract: A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.

公开(公告)号：US11670567B2

公开(公告)日：2023-06-06

申请号：US16924206

申请日：2020-07-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Liang Liao ,  Purakh Raj Verma ,  Ching-Yang Wen ,  Chee Hau Ng

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/3735 ,  H01L21/4871 ,  H01L23/15 ,  H01L23/3736

Abstract: A semiconductor structure includes a glass substrate and a device wafer. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.

公开(公告)号：US11658087B2

公开(公告)日：2023-05-23

申请号：US17080858

申请日：2020-10-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/367 ,  H01L21/48

CPC classification number: H01L23/367 ,  H01L21/4803

Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.

公开(公告)号：US20230058468A1

公开(公告)日：2023-02-23

申请号：US17409756

申请日：2021-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： BO TAO ,  RUNSHUN WANG ,  Li Wang ,  Ching-Yang Wen ,  Purakh Raj Verma ,  DONG YIN ,  Jian Xie

IPC: H01L21/768

Abstract: A method of fabricating an air gap includes receiving a first thickness information of an inter-metal dielectric layer formed on a substrate and receiving a second thickness information of an inter-layer dielectric layer formed on the substrate. Then, a first etching is performed, wherein the first etching includes etch the inter-metal dielectric layer based on a first etching control value corresponding to the first thickness information. After the first etching, a second etching is performed to etch the inter-layer dielectric layer based on a second etching control value corresponding to the second thickness information.