公开(公告)号：US20170243977A1

公开(公告)日：2017-08-24

申请号：US15064618

申请日：2016-03-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Yao Lin ,  Ling-Chun Chou ,  Kun-Hsien Lee

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/167 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4236 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/7848

Abstract: The present invention provides a FinFET device, including at least one fin structure, wherein the fin structure has a first-type well region, and a second-type well region adjacent to the first-type well region, a trench located in the fin structure and disposed between the first-type well region and the second-type well region, an insulating layer disposed in the trench, and a metal gate crossing over and disposed on the insulating layer.

公开(公告)号：US10897131B2

公开(公告)日：2021-01-19

申请号：US15878421

申请日：2018-01-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Liao ,  Ting-Yao Lin ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H02H9/00 ,  H02H9/04 ,  H02H1/00 ,  H01L27/02 ,  H01L27/06

Abstract: An electrostatic discharge (ESD) protection circuit has a first power node, a second power node, an ESD detect circuit, an ESD device and a voltage controlled switch. The ESD detect circuit is coupled between the first power node and the second power node for detecting an ESD current to output a control signal at a output terminal of the ESD detect circuit. The ESD device is coupled between the first power node and the second power node for leaking the ESD current. The voltage controlled switch is used to couple a body of the ESD device to the second power node according to at least a voltage level of the control signal.

公开(公告)号：US10903205B2

公开(公告)日：2021-01-26

申请号：US16394967

申请日：2019-04-25

Applicant: United Microelectronics Corp.

Inventor： Ting-Yao Lin ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/66

Abstract: A semiconductor device of ESD protection includes a first P-type well in a substrate to receive a protected terminal and a first N-type well abutting the first P-type well in the substrate. A second P-type well abutting the first N-type well is in the substrate. A second N-type well abutting the second P-type well is in the substrate. A detective circuit device is formed on a surface of the substrate, having an input terminal to receive the protected terminal and an output terminal to provide a trigger voltage to the first N-type well. A first route structure is in the substrate, on a sidewall and a bottom of the first P-type well to connect to a bottom of the first N-type well. A second route structure is in the substrate, on sidewall and bottom of the second N-type well, to connect to a bottom of the second P-type well.

公开(公告)号：US11257807B2

公开(公告)日：2022-02-22

申请号：US17111220

申请日：2020-12-03

Applicant: United Microelectronics Corp.

Inventor： Ting-Yao Lin ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

Abstract: A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.

公开(公告)号：US20190229531A1

公开(公告)日：2019-07-25

申请号：US15878421

申请日：2018-01-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Liao ,  Ting-Yao Lin ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H02H9/04 ,  H02H1/00 ,  H01L27/02

Abstract: An electrostatic discharge (ESD) protection circuit has a first power node, a second power node, an ESD detect circuit, an ESD device and a voltage controlled switch. The ESD detect circuit is coupled between the first power node and the second power node for detecting an ESD current to output a control signal at a output terminal of the ESD detect circuit. The ESD device is coupled between the first power node and the second power node for leaking the ESD current. The voltage controlled switch is used to couple a body of the ESD device to the second power node according to at least a voltage level of the control signal.

公开(公告)号：US20210091069A1

公开(公告)日：2021-03-25

申请号：US17111220

申请日：2020-12-03

Applicant: United Microelectronics Corp.

Inventor： Ting-Yao Lin ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

Abstract: A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.

公开(公告)号：US20200343238A1

公开(公告)日：2020-10-29

申请号：US16394967

申请日：2019-04-25

Applicant: United Microelectronics Corp.

Inventor： Ting-Yao Lin ,  Chun Chiang ,  Ping-Chen Chang ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/66

Abstract: A semiconductor device of ESD protection includes a first P-type well in a substrate to receive a protected terminal and a first N-type well abutting the first P-type well in the substrate. A second P-type well abutting the first N-type well is in the substrate. A second N-type well abutting the second P-type well is in the substrate. A detective circuit device is formed on a surface of the substrate, having an input terminal to receive the protected terminal and an output terminal to provide a trigger voltage to the first N-type well. A first route structure is in the substrate, on a sidewall and a bottom of the first P-type well to connect to a bottom of the first N-type well. A second route structure is in the substrate, on sidewall and bottom of the second N-type well, to connect to a bottom of the second P-type well.

公开(公告)号：US09799770B2

公开(公告)日：2017-10-24

申请号：US15064618

申请日：2016-03-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Yao Lin ,  Ling-Chun Chou ,  Kun-Hsien Lee

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/167 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4236 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/7848

Abstract: The present invention provides a FinFET device, including at least one fin structure, wherein the fin structure has a first-type well region, and a second-type well region adjacent to the first-type well region, a trench located in the fin structure and disposed between the first-type well region and the second-type well region, an insulating layer disposed in the trench, and a metal gate crossing over and disposed on the insulating layer.