Hypervisor context switching using a trampoline scheme in processors having more than two hierarchical privilege levels

    公开(公告)号:US10019275B2

    公开(公告)日:2018-07-10

    申请号:US14312175

    申请日:2014-06-23

    Applicant: VMware, Inc.

    Abstract: In a virtualized computer system operable in more than two hierarchical privilege levels, components of a hypervisor, which include a virtual machine kernel and virtual machine monitors (VMMs), are assigned to different privilege levels. The virtual machine kernel operates at a low privilege level to be able to exploit certain features provided by the low privilege level, and the VMMs operate at a high privilege level to support execution of virtual machines. Upon determining that a context switch from the virtual machine kernel to a VMM is to be performed, the computer system exits the low privilege level, and enters the high privilege level to execute a trampoline that supports context switches to VMMs, such as state changes, and then the VMM. The trampoline is deactivated after execution control is switched to the VMM.

    Device simulation in a secure mode supported by hardware architectures

    公开(公告)号:US09952887B2

    公开(公告)日:2018-04-24

    申请号:US14312249

    申请日:2014-06-23

    Applicant: VMware, Inc.

    CPC classification number: G06F9/45516 G06F9/45533 G06F21/74

    Abstract: A secure mode of a computer system is used to provide simulated devices. In operation, if an instruction executing in a non-secure mode accesses a simulated device, then a resulting exception is forwarded to a secure monitor executing in the secure mode. Based on the address accessed by the instruction, the secure monitor identifies the device and simulates the instruction. The secure monitor executes independently of other applications included in the computer system, and does not rely on any hardware virtualization capabilities of the computer system.

    Configuration profile validation on iOS based on root certificate validation
    4.
    发明授权
    Configuration profile validation on iOS based on root certificate validation 有权
    基于根证书验证的iOS配置配置文件验证

    公开(公告)号:US09077725B2

    公开(公告)日:2015-07-07

    申请号:US13848333

    申请日:2013-03-21

    Applicant: VMware, Inc.

    Abstract: An application management agent running on a wireless communications device restricts access to device functionality (e.g., applications and device features) unless the application management agent has determined that a particular configuration profile has been installed on the device (after which the application management agent permits access to device functionality, and an operating system of the device enforces policy settings specified in the configuration profile). The application management agent confirms the presence of the configuration profile by using a validation certificate to validate against a root certificate embedded in a configuration profile installed on the device. The configuration profile is configured to be non-removable, so it cannot be remove or updated, except by another configuration profile signed by the same authority. Validation against the embedded root certificate thereby implicitly confirms the presence of the configuration profile and validates the content of the configuration profile.

    Abstract translation: 运行在无线通信设备上的应用管理代理限制对设备功能的访问(例如,应用和设备特征),除非应用管理代理已经确定特定配置简档已经安装在设备上(之后应用管理代理允许访问 到设备功能,并且设备的操作系统实施配置简档中指定的策略设置)。 应用程序管理代理通过使用验证证书来验证配置配置文件的存在,以验证嵌入在设备上安装的配置文件中的根证书。 配置配置文件配置为不可移动,因此不能删除或更新,除了由同一个权限签署的其他配置配置文件外。 针对嵌入式根证书的验证从而隐含地确认配置配置文件的存在并验证配置配置文件的内容。

    Exposing memory-mapped IO devices to drivers by emulating PCI bus and PCI device configuration space

    公开(公告)号:US10534732B2

    公开(公告)日:2020-01-14

    申请号:US14754569

    申请日:2015-06-29

    Applicant: VMware, Inc.

    Abstract: Devices are emulated as PCI devices so that existing PCI drivers can be used for the devices. This is accomplished by creating a shim PCI device with a emulated PCI configuration space, accessed via a emulated PCI Extended Configuration Access Mechanism (ECAM) space which is emulated by accesses to trapped unbacked memory addresses. When system software accesses the PCI ECAM space to probe for PCI configuration data or program base address registers of the PCI ECAM space, an exception is raised and the exception is handled by a secure monitor that is executing at a higher privilege level than the system software. The secure monitor in handling the exception emulates the PCI configuration space access of the emulated PCI device corresponding to the ECAM address accessed, such that system software may discover the device and bind and appropriately configure a PCI driver to it with the right IRQ and memory base ranges.

    Hypervisor context switching using TLB tags in processors having more than two hierarchical privilege levels

    公开(公告)号:US10162655B2

    公开(公告)日:2018-12-25

    申请号:US14312225

    申请日:2014-06-23

    Applicant: VMware, Inc.

    Abstract: In a virtualized computer system operable in more than two hierarchical privilege levels, components of a hypervisor, which include a virtual machine kernel and virtual machine monitors (VMMs), are assigned to different privilege levels. The virtual machine kernel operates at a low privilege level to be able to exploit certain features provided by the low privilege level, and the VMMs operate at a high privilege level to support execution of virtual machines. Upon determining that a context switch from the virtual machine kernel to a VMM is to be performed, the computer system exits the low privilege level, and enters the high privilege level to execute a trampoline that supports context switches to VMMs, such as state changes, and then the VMM. The trampoline is deactivated after execution control is switched to the VMM.

    Hypervisor backdoor interface
    7.
    发明授权

    公开(公告)号:US10067784B2

    公开(公告)日:2018-09-04

    申请号:US15184455

    申请日:2016-06-16

    Applicant: VMware, Inc.

    Abstract: A method of providing a backdoor interface between software executing in a virtual machine and a hypervisor executing on a computing system that supports the virtual machine includes trapping, at the hypervisor, an exception generated in response to execution of a debug instruction on a central processing unit (CPU) by the software; identifying, by an exception handler of the hypervisor handling the exception, an equivalence between an immediate operand of the debug instruction and a predefined value; and invoking, in response to the equivalence, a backdoor service of the hypervisor using state of at least one register of the CPU as parametric input, the state being set by the software prior to executing the debug instruction.

    Remote Provisioning of Hosts in Public Clouds

    公开(公告)号:US20180095771A1

    公开(公告)日:2018-04-05

    申请号:US15282893

    申请日:2016-09-30

    Applicant: VMware, Inc.

    Abstract: Examples provide for automatically provisioning hosts in a cloud environment. A cloud daemon generates a cloud host-state configuration, for a given cloud instance of a host, stored on a cloud metadata service prior to first boot of the given cloud instance of the host. A first boot of a plurality of cloud instances of hosts is performed using a stateless, master boot image lacking host-specific configuration data. On completion of the first boot of a given cloud instance of a host, the cloud host-state configuration is installed on the master boot image to generate a self-configured boot image including host-specific configuration data for the given cloud instance of the host. A second boot is performed on the given cloud instance of the host by executing the self-configured boot image to automatically provision the given cloud instance of the host in the cloud environment.

    IMPLEMENTING PSEUDO NON-MASKING INTERRUPTS BEHAVIOR USING A PRIORITY INTERRUPT CONTROLLER
    9.
    发明申请
    IMPLEMENTING PSEUDO NON-MASKING INTERRUPTS BEHAVIOR USING A PRIORITY INTERRUPT CONTROLLER 有权
    使用优先中断控制器实现PSEUDO非屏蔽中断行为

    公开(公告)号:US20160378543A1

    公开(公告)日:2016-12-29

    申请号:US14876831

    申请日:2015-10-07

    Applicant: VMWARE, INC.

    CPC classification number: G06F9/4818 G06F13/26

    Abstract: A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts. The method includes the steps of obtaining an interrupt vector corresponding to a received interrupt, and if the received interrupt is a regular interrupt, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing a regular interrupt handler using the interrupt vector, and disabling interrupts in the processor. On the other hand, if the received interrupt is a PNMI, a PNMI interrupt handler is executed using the interrupt vector as an input thereto.

    Abstract translation: 提供了一种用于处理处理器中断的方法,所述中断包括具有优先级范围的规则中断和比任何常规中断更高优先级的伪不可屏蔽中断(PNMI)。 该方法包括获得与接收到的中断相对应的中断向量的步骤,并且如果接收到的中断是常规中断,则允许处理器中的中断,使得在处理常规中断时可以接收PNMI,执行常规中断处理程序使用 中断向量和禁用处理器中断。 另一方面,如果接收到的中断是PNMI,则使用中断向量作为其输入来执行PNMI中断处理程序。

    Secondary CPU MMU initialization using page fault exception
    10.
    发明授权
    Secondary CPU MMU initialization using page fault exception 有权
    辅助CPU MMU初始化使用页面错误异常

    公开(公告)号:US09383935B1

    公开(公告)日:2016-07-05

    申请号:US14572505

    申请日:2014-12-16

    Applicant: VMware, Inc.

    Abstract: In a computer system with multiple central processing units (CPUs), initialization of a memory management unit (MMU) for a secondary CPU is performed using an exception generated by the MMU. In general, this technique leverages the exception handling features of the secondary CPU to switch the CPU from executing secondary CPU initialization code with the MMU “off” to executing secondary CPU initialization code with the MMU “on.” Advantageously, in contrast to conventional techniques for MMU initialization, this exception-based technique does not require identity mapping of the secondary CPU initialization code to ensure proper execution of the secondary CPU initialization code.

    Abstract translation: 在具有多个中央处理单元(CPU)的计算机系统中,使用由MMU生成的异常来执行用于辅助CPU的存储器管理单元(MMU)的初始化。 一般来说,这种技术利用辅助CPU的异常处理功能,将CPU从执行辅助CPU初始化代码的MMU“关闭”切换到执行次级CPU初始化代码,MMU“打开”。有利的是,与传统技术 对于MMU初始化,这种基于异常的技术不需要辅助CPU初始化代码的身份映射,以确保辅助CPU初始化代码的正确执行。

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