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公开(公告)号：US08344472B2
公开(公告)日：2013-01-01
申请号：US12750151
申请日：2010-03-30
申请人： Vishnu K. Khemka , Tahir A. Khan , Weixiao Huang , Ronghua Zhu
发明人： Vishnu K. Khemka , Tahir A. Khan , Weixiao Huang , Ronghua Zhu
IPC分类号： H01L29/66
CPC分类号： H01L27/098 , H01L27/0705 , H01L27/085 , H01L27/088 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers may be susceptible to noise coupling into the floating buried layers. In IGFETS this is reduced or eliminated by providing a normally-ON switch (80, 80′) coupling the buried layer (102, 142, 172, 202) and the IGFET source (22, 42) or drain (24, 44). When the transistor (71, 91) is OFF, this clamps the buried layer voltage and substantially prevents noise coupling thereto. When the drain-source voltage VDS exceeds the switch's (80, 80′) threshold voltage Vt, it turns OFF, allowing the buried layer (102, 142, 172, 202) to float, and thereby resume normal transistor action without degrading the breakdown voltage or ON-resistance. In a preferred embodiment, a normally-ON lateral JFET (801, 801′, 801-1, 801-2, 801-3) conveniently provides this switching function. The lateral JFET (801-3) can be included in the device (70, 70′, 90, 90′) by mask changes without adding or customizing any process steps, thereby providing the improved noise resistance without significant increase in manufacturing cost. The improvement applies to both P (90-1) and N channel (70-1, 70-2, 70-3) transistors and is particularly useful for LDMOS devices.
摘要翻译： 使用浮置掩埋层的晶体管（21,41）可能易于与浮动掩埋层的噪声耦合。 在IGFETS中，通过提供耦合埋层（102,142,172,202）和IGFET源（22,42）或漏极（24,44）的常开开关（80,80'）来减少或消除这种情况。 当晶体管（71,91）为OFF时，这夹着埋层电压并且基本上防止与其耦合的噪声。 当漏极 - 源极电压V DS超过开关（80,80'）阈值电压Vt时，它变为OFF，允许埋层（102,142,172,202）浮起，从而恢复正常的晶体管作用而不降低击穿 电压或导通电阻。 在优选实施例中，正向导通的横向JFET（801,801'，801-1,801-2,801-3）方便地提供该开关功能。 横向JFET（801-3）可以通过掩模改变而被包括在设备（70,70'，90,90'）中，而不需要添加或定制任何工艺步骤，从而提供改进的抗噪声性，而不会显着增加制造成本。 该改进适用于P（90-1）和N通道（70-1,70-2,70-3）晶体管，并且对于LDMOS器件特别有用。
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公开(公告)号：US08338872B2
公开(公告)日：2012-12-25
申请号：US12750166
申请日：2010-03-30
CPC分类号： H01L27/0705 , H01L27/088 , H01L27/098 , H01L29/0653 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69′) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94′) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94′) may be external to the transistor (69, 69′), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69′-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.
摘要翻译： 使用浮动掩埋层（BL）（72）的晶体管（21,41）可以显示出显着小于（BVdss）DC的瞬态击穿电压（BVdss）TR。 发现这是因为浮动BL（72）不能快速跟随施加的瞬态，导致装置内的局部电场暂时超过雪崩状况。 通过包括将浮动BL（72）耦合到无论哪个高侧端子（...）的电荷泵电容（94,94'），可以将这种晶体管（69.69'）的（BVdss）TR提高到等于或超过（BVdss） 28，47）接收瞬态。 电荷泵电容（94,94'）可以在晶体管（69,69'）的外部，可以形成在器件表面（71）上，或者可以形成在晶体管（69-3,69' 3）使用分离延伸到BL（72）的直流隔离沉降片区域（86,88）的电介质深沟槽隔离壁（100）。 该改进对于LDMOS器件特别有用。
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公开(公告)号：US20110241092A1
公开(公告)日：2011-10-06
申请号：US12750166
申请日：2010-03-30
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0705 , H01L27/088 , H01L27/098 , H01L29/0653 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69′) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94′) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94′) may be external to the transistor (69, 69′), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69′-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.
摘要翻译： 使用浮动掩埋层（BL）（72）的晶体管（21,41）可以显示出显着小于（BVdss）DC的瞬态击穿电压（BVdss）TR。 发现这是因为浮动BL（72）不能快速跟随施加的瞬态，导致装置内的局部电场暂时超过雪崩状况。 通过包括将浮动BL（72）耦合到无论哪个高侧端子（...）的电荷泵电容（94,94'），可以将这种晶体管（69.69'）的（BVdss）TR提高到等于或超过（BVdss） 28，47）接收瞬态。 电荷泵电容（94,94'）可以在晶体管（69,69'）的外部，可以形成在器件表面（71）上，或者可以形成在晶体管（69-3,69' 3）使用分离延伸到BL（72）的直流隔离沉降片区域（86,88）的电介质深沟槽隔离壁（100）。 该改进对于LDMOS器件特别有用。
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公开(公告)号：US08193585B2
公开(公告)日：2012-06-05
申请号：US12608586
申请日：2009-10-29
IPC分类号： H01L29/66
CPC分类号： H01L29/7835 , H01L29/063 , H01L29/0653 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： Methods and apparatus are provided for fabricating a semiconductor device structure. The semiconductor device structure comprises a buried region having a first conductivity type, a first region having a second conductivity type overlying the buried region, a source region having the first conductivity type overlying the first region, and a drain region having the first conductivity type overlying the first region. The semiconductor device structure further comprises a second region having the first conductivity type overlying the buried region, the second region abutting the buried region to form an electrical contact with the buried region, and a first resistance configured electrically in series with the second region and the buried region. The combined series resistance of the first resistance and the second region is greater than a resistance of the buried region.
摘要翻译： 提供了用于制造半导体器件结构的方法和装置。 半导体器件结构包括具有第一导电类型的掩埋区域，覆盖掩埋区域的具有第二导电类型的第一区域，覆盖第一区域的具有第一导电类型的源极区域和覆盖第一导电类型的漏极区域 第一个地区。 所述半导体器件结构还包括具有覆盖所述掩埋区域的所述第一导电类型的第二区域，所述第二区域邻接所述掩埋区域以与所述掩埋区域形成电接触，以及与所述第二区域串联构造的第一电阻和 埋地区 第一电阻和第二区域的组合串联电阻大于埋入区域的电阻。
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公开(公告)号：US20110241083A1
公开(公告)日：2011-10-06
申请号：US12750151
申请日：2010-03-30
申请人： Vishnu K. Khemka , Tahir A. Khan , Weixiao Huang , Ronghua Zhu
发明人： Vishnu K. Khemka , Tahir A. Khan , Weixiao Huang , Ronghua Zhu
IPC分类号： H01L27/085 , H01L21/8232
CPC分类号： H01L27/098 , H01L27/0705 , H01L27/085 , H01L27/088 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers may be susceptible to noise coupling into the floating buried layers. In IGFETS this is reduced or eliminated by providing a normally-ON switch (80, 80′) coupling the buried layer (102, 142, 172, 202) and the IGFET source (22, 42) or drain (24, 44). When the transistor (71, 91) is OFF, this clamps the buried layer voltage and substantially prevents noise coupling thereto. When the drain-source voltage VDS exceeds the switch's (80, 80′) threshold voltage Vt, it turns OFF, allowing the buried layer (102, 142, 172, 202) to float, and thereby resume normal transistor action without degrading the breakdown voltage or ON-resistance. In a preferred embodiment, a normally-ON lateral JFET (801, 801′, 801-1, 801-2, 801-3) conveniently provides this switching function. The lateral JFET (801-3) can be included in the device (70, 70′, 90, 90′) by mask changes without adding or customizing any process steps, thereby providing the improved noise resistance without significant increase in manufacturing cost. The improvement applies to both P (90-1) and N channel (70-1, 70-2, 70-3) transistors and is particularly useful for LDMOS devices.
摘要翻译： 使用浮置掩埋层的晶体管（21,41）可能易于与浮动掩埋层的噪声耦合。 在IGFETS中，通过提供耦合埋层（102,142,172,202）和IGFET源（22,42）或漏极（24,44）的常开开关（80,80'）来减少或消除这种情况。 当晶体管（71,91）为OFF时，这夹着埋层电压并且基本上防止与其耦合的噪声。 当漏极 - 源极电压V DS超过开关（80,80'）阈值电压Vt时，它变为OFF，允许埋层（102,142,172,202）浮起，从而恢复正常的晶体管作用而不降低击穿 电压或导通电阻。 在优选实施例中，正向导通的横向JFET（801,801'，801-1,801-2,801-3）方便地提供该开关功能。 横向JFET（801-3）可以通过掩模改变而被包括在设备（70,70'，90,90'）中，而不需要添加或定制任何工艺步骤，从而提供改进的抗噪声性，而不会显着增加制造成本。 该改进适用于P（90-1）和N通道（70-1,70-2,70-3）晶体管，并且对于LDMOS器件特别有用。
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公开(公告)号：US20110101425A1
公开(公告)日：2011-05-05
申请号：US12608586
申请日：2009-10-29
IPC分类号： H01L29/78 , H01L21/8232
CPC分类号： H01L29/7835 , H01L29/063 , H01L29/0653 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： Methods and apparatus are provided for fabricating a semiconductor device structure. The semiconductor device structure comprises a buried region having a first conductivity type, a first region having a second conductivity type overlying the buried region, a source region having the first conductivity type overlying the first region, and a drain region having the first conductivity type overlying the first region. The semiconductor device structure further comprises a second region having the first conductivity type overlying the buried region, the second region abutting the buried region to form an electrical contact with the buried region, and a first resistance configured electrically in series with the second region and the buried region. The combined series resistance of the first resistance and the second region is greater than a resistance of the buried region.
摘要翻译： 提供了用于制造半导体器件结构的方法和装置。 半导体器件结构包括具有第一导电类型的掩埋区域，覆盖掩埋区域的具有第二导电类型的第一区域，覆盖第一区域的具有第一导电类型的源极区域和覆盖第一导电类型的漏极区域 第一个地区。 所述半导体器件结构还包括具有覆盖所述掩埋区域的所述第一导电类型的第二区域，所述第二区域邻接所述掩埋区域以与所述掩埋区域形成电接触，以及与所述第二区域串联构造的第一电阻和 埋地区。 第一电阻和第二区域的组合串联电阻大于埋入区域的电阻。
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公开(公告)号：US08384184B2
公开(公告)日：2013-02-26
申请号：US12882899
申请日：2010-09-15
IPC分类号： H01L29/78
CPC分类号： H01L29/66681 , H01L21/02107 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.
摘要翻译： 这里介绍一种半导体器件和相关的制造工艺。 该器件包括支撑衬底，覆盖在支撑衬底上的掩埋氧化物层，位于掩埋氧化物层上方并具有第一导电类型的第一半导体区域。 该器件还包括第二，第三，第四和第五半导体区域。 第二半导体区域位于第一半导体区域的上方，具有第二导电型。 第三半导体区域位于第二半导体区域的上方，具有第一导电型。 第四半导体区域位于第三半导体区域的上方，具有第二导电型。 第五半导体区域延伸穿过第四半导体区域和第三半导体区域到第二半导体区域，并且具有第二导电类型。
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8.发明申请公开(公告)号：US20130009243A1
公开(公告)日：2013-01-10
申请号：US13614722
申请日：2012-09-13
申请人： Tahir A. Khan , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/1083 , H01L29/66659
摘要： A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed.
摘要翻译： 横向双扩散金属氧化物半导体器件包括具有第一导电性的阱区，具有第一导电类型的第一载流子再分布区，其中第二阱区位于阱区之下，以及在第二阱区下面的高掺杂掩埋层 。 高掺杂掩埋层具有第一导电类型，并且其掺杂剂浓度小于阱区的掺杂浓度，并且小于第一载流子再分布区的掺杂浓度，并且掩埋层与第一阱区相连。 此外，公开了可以使用外延生长的横向双重扩散金属氧化物半导体器件的形成方法。
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公开(公告)号：US20090174030A1
公开(公告)日：2009-07-09
申请号：US11969600
申请日：2008-01-04
申请人： Tahir A. Khan , Amitava Bose , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Amitava Bose , Vishnu K. Khemka , Ronghua Zhu
IPC分类号： H01L21/283 , H01L29/94
CPC分类号： H01L29/94 , H01L21/86 , H01L29/20 , H01L29/22 , H01L29/66181
摘要： Method (200) and apparatus (30, 50-53) are described for MOS capacitors (MOS CAPs). The apparatus (30, 50-53) comprises a substrate (31) having Ohmically coupled N and P semiconductor regions (32, 34; 54, 56; 92, 94) covered by a dielectric (35, 57, 95). A conductive electrode (36, 58, 96) overlies the dielectric (35, 57, 95) above these N and P regions (32, 34; 54, 56; 92, 94). Use of the Ohmically coupled N and P regions (32, 34; 54, 56; 92, 94) substantially reduces the variation (40, 64, 70, 80) of capacitance with applied voltage associated with ordinary MOS CAPs. When these N and P regions (32, 34; 54, 56; 92, 94) have unequal doping, the capacitance variation (40, 64, 70, 80) may still be substantially compensated by adjusting the properties of the dielectric (57, 95) above the N and P regions (54, 56; 92, 94) and/or relative areas of the N and P regions (54, 56; 92, 94) or both. Accordingly, such MOS CAPS may be more easily integrated with other semiconductor devices with minimal or no disturbance to the established integrated circuit (IC) manufacturing process and without significantly increasing the occupied area beyond that required for a conventional MOS CAP.
摘要翻译： 对于MOS电容器（MOS CAP）描述了方法（200）和装置（30,50-53）。 装置（30,50-53）包括具有由电介质（35,57,95）覆盖的欧姆耦合的N和P半导体区域（32,34; 54,56; 92,94）的衬底（31）。 导电电极（36,58,96）覆盖在这些N和P区域（32,34; 54,56; 92,94）上方的电介质（35,57,95）上。 使用欧姆耦合的N和P区域（32,34; 54,56; 92,94）通过与普通MOS CAP相关联的施加电压基本上减小电容的变化（40,64,70,80）。 当这些N和P区域（32,34; 54,56; 92,94）具有不同的掺杂时，电容变化（40,64,70,80）仍然可以通过调节电介质的性质（57， （54,56; 92,94）的N区域和/或P区域（54,56; 92,94）或两者的相对区域之间。 因此，这样的MOS CAPS可以更容易地与其他半导体器件集成，对所建立的集成电路（IC）制造过程具有最小或没有干扰，并且不会显着地增加超过常规MOS CAP所需的占用面积。
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10.发明授权公开(公告)号：US08907419B2
公开(公告)日：2014-12-09
申请号：US13614722
申请日：2012-09-13
申请人： Tahir A. Khan , Vishnu K. Khemka , Ronghua Zhu
发明人： Tahir A. Khan , Vishnu K. Khemka , Ronghua Zhu
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/1083 , H01L29/66659
摘要： A laterally double diffused metal oxide semiconductor device includes a well region having a first conductivity, a first carrier redistribution region having the first conductivity type, wherein the second well region is under the well region, and a highly doped buried layer under the second well region. The highly doped buried layer has the first conductivity type and has a dopant concentration less than that of the well region and less than that of the first carrier redistribution region, and the buried layer is tied to the first well region. In addition, a method for forming the laterally double diffused metal oxide semiconductor device, which may use epitaxial growth, is disclosed.
摘要翻译： 横向双扩散金属氧化物半导体器件包括具有第一导电性的阱区，具有第一导电类型的第一载流子再分布区，其中第二阱区位于阱区之下，以及在第二阱区下面的高掺杂掩埋层 。 高掺杂掩埋层具有第一导电类型，并且其掺杂剂浓度小于阱区的掺杂浓度，并且小于第一载流子再分布区的掺杂浓度，并且掩埋层与第一阱区相连。 此外，公开了可以使用外延生长的横向双重扩散金属氧化物半导体器件的形成方法。
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