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公开(公告)号：US08338872B2
公开(公告)日：2012-12-25
申请号：US12750166
申请日：2010-03-30
CPC分类号： H01L27/0705 , H01L27/088 , H01L27/098 , H01L29/0653 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69′) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94′) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94′) may be external to the transistor (69, 69′), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69′-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.
摘要翻译： 使用浮动掩埋层（BL）（72）的晶体管（21,41）可以显示出显着小于（BVdss）DC的瞬态击穿电压（BVdss）TR。 发现这是因为浮动BL（72）不能快速跟随施加的瞬态，导致装置内的局部电场暂时超过雪崩状况。 通过包括将浮动BL（72）耦合到无论哪个高侧端子（...）的电荷泵电容（94,94'），可以将这种晶体管（69.69'）的（BVdss）TR提高到等于或超过（BVdss） 28，47）接收瞬态。 电荷泵电容（94,94'）可以在晶体管（69,69'）的外部，可以形成在器件表面（71）上，或者可以形成在晶体管（69-3,69' 3）使用分离延伸到BL（72）的直流隔离沉降片区域（86,88）的电介质深沟槽隔离壁（100）。 该改进对于LDMOS器件特别有用。
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公开(公告)号：US20110241092A1
公开(公告)日：2011-10-06
申请号：US12750166
申请日：2010-03-30
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0705 , H01L27/088 , H01L27/098 , H01L29/0653 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69′) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94′) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94′) may be external to the transistor (69, 69′), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69′-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.
摘要翻译： 使用浮动掩埋层（BL）（72）的晶体管（21,41）可以显示出显着小于（BVdss）DC的瞬态击穿电压（BVdss）TR。 发现这是因为浮动BL（72）不能快速跟随施加的瞬态，导致装置内的局部电场暂时超过雪崩状况。 通过包括将浮动BL（72）耦合到无论哪个高侧端子（...）的电荷泵电容（94,94'），可以将这种晶体管（69.69'）的（BVdss）TR提高到等于或超过（BVdss） 28，47）接收瞬态。 电荷泵电容（94,94'）可以在晶体管（69,69'）的外部，可以形成在器件表面（71）上，或者可以形成在晶体管（69-3,69' 3）使用分离延伸到BL（72）的直流隔离沉降片区域（86,88）的电介质深沟槽隔离壁（100）。 该改进对于LDMOS器件特别有用。
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公开(公告)号：US08193585B2
公开(公告)日：2012-06-05
申请号：US12608586
申请日：2009-10-29
IPC分类号： H01L29/66
CPC分类号： H01L29/7835 , H01L29/063 , H01L29/0653 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： Methods and apparatus are provided for fabricating a semiconductor device structure. The semiconductor device structure comprises a buried region having a first conductivity type, a first region having a second conductivity type overlying the buried region, a source region having the first conductivity type overlying the first region, and a drain region having the first conductivity type overlying the first region. The semiconductor device structure further comprises a second region having the first conductivity type overlying the buried region, the second region abutting the buried region to form an electrical contact with the buried region, and a first resistance configured electrically in series with the second region and the buried region. The combined series resistance of the first resistance and the second region is greater than a resistance of the buried region.
摘要翻译： 提供了用于制造半导体器件结构的方法和装置。 半导体器件结构包括具有第一导电类型的掩埋区域，覆盖掩埋区域的具有第二导电类型的第一区域，覆盖第一区域的具有第一导电类型的源极区域和覆盖第一导电类型的漏极区域 第一个地区。 所述半导体器件结构还包括具有覆盖所述掩埋区域的所述第一导电类型的第二区域，所述第二区域邻接所述掩埋区域以与所述掩埋区域形成电接触，以及与所述第二区域串联构造的第一电阻和 埋地区 第一电阻和第二区域的组合串联电阻大于埋入区域的电阻。
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公开(公告)号：US20110101425A1
公开(公告)日：2011-05-05
申请号：US12608586
申请日：2009-10-29
IPC分类号： H01L29/78 , H01L21/8232
CPC分类号： H01L29/7835 , H01L29/063 , H01L29/0653 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： Methods and apparatus are provided for fabricating a semiconductor device structure. The semiconductor device structure comprises a buried region having a first conductivity type, a first region having a second conductivity type overlying the buried region, a source region having the first conductivity type overlying the first region, and a drain region having the first conductivity type overlying the first region. The semiconductor device structure further comprises a second region having the first conductivity type overlying the buried region, the second region abutting the buried region to form an electrical contact with the buried region, and a first resistance configured electrically in series with the second region and the buried region. The combined series resistance of the first resistance and the second region is greater than a resistance of the buried region.
摘要翻译： 提供了用于制造半导体器件结构的方法和装置。 半导体器件结构包括具有第一导电类型的掩埋区域，覆盖掩埋区域的具有第二导电类型的第一区域，覆盖第一区域的具有第一导电类型的源极区域和覆盖第一导电类型的漏极区域 第一个地区。 所述半导体器件结构还包括具有覆盖所述掩埋区域的所述第一导电类型的第二区域，所述第二区域邻接所述掩埋区域以与所述掩埋区域形成电接触，以及与所述第二区域串联构造的第一电阻和 埋地区。 第一电阻和第二区域的组合串联电阻大于埋入区域的电阻。
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公开(公告)号：US08344472B2
公开(公告)日：2013-01-01
申请号：US12750151
申请日：2010-03-30
申请人： Vishnu K. Khemka , Tahir A. Khan , Weixiao Huang , Ronghua Zhu
发明人： Vishnu K. Khemka , Tahir A. Khan , Weixiao Huang , Ronghua Zhu
IPC分类号： H01L29/66
CPC分类号： H01L27/098 , H01L27/0705 , H01L27/085 , H01L27/088 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers may be susceptible to noise coupling into the floating buried layers. In IGFETS this is reduced or eliminated by providing a normally-ON switch (80, 80′) coupling the buried layer (102, 142, 172, 202) and the IGFET source (22, 42) or drain (24, 44). When the transistor (71, 91) is OFF, this clamps the buried layer voltage and substantially prevents noise coupling thereto. When the drain-source voltage VDS exceeds the switch's (80, 80′) threshold voltage Vt, it turns OFF, allowing the buried layer (102, 142, 172, 202) to float, and thereby resume normal transistor action without degrading the breakdown voltage or ON-resistance. In a preferred embodiment, a normally-ON lateral JFET (801, 801′, 801-1, 801-2, 801-3) conveniently provides this switching function. The lateral JFET (801-3) can be included in the device (70, 70′, 90, 90′) by mask changes without adding or customizing any process steps, thereby providing the improved noise resistance without significant increase in manufacturing cost. The improvement applies to both P (90-1) and N channel (70-1, 70-2, 70-3) transistors and is particularly useful for LDMOS devices.
摘要翻译： 使用浮置掩埋层的晶体管（21,41）可能易于与浮动掩埋层的噪声耦合。 在IGFETS中，通过提供耦合埋层（102,142,172,202）和IGFET源（22,42）或漏极（24,44）的常开开关（80,80'）来减少或消除这种情况。 当晶体管（71,91）为OFF时，这夹着埋层电压并且基本上防止与其耦合的噪声。 当漏极 - 源极电压V DS超过开关（80,80'）阈值电压Vt时，它变为OFF，允许埋层（102,142,172,202）浮起，从而恢复正常的晶体管作用而不降低击穿 电压或导通电阻。 在优选实施例中，正向导通的横向JFET（801,801'，801-1,801-2,801-3）方便地提供该开关功能。 横向JFET（801-3）可以通过掩模改变而被包括在设备（70,70'，90,90'）中，而不需要添加或定制任何工艺步骤，从而提供改进的抗噪声性，而不会显着增加制造成本。 该改进适用于P（90-1）和N通道（70-1,70-2,70-3）晶体管，并且对于LDMOS器件特别有用。
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公开(公告)号：US20110241083A1
公开(公告)日：2011-10-06
申请号：US12750151
申请日：2010-03-30
申请人： Vishnu K. Khemka , Tahir A. Khan , Weixiao Huang , Ronghua Zhu
发明人： Vishnu K. Khemka , Tahir A. Khan , Weixiao Huang , Ronghua Zhu
IPC分类号： H01L27/085 , H01L21/8232
CPC分类号： H01L27/098 , H01L27/0705 , H01L27/085 , H01L27/088 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers may be susceptible to noise coupling into the floating buried layers. In IGFETS this is reduced or eliminated by providing a normally-ON switch (80, 80′) coupling the buried layer (102, 142, 172, 202) and the IGFET source (22, 42) or drain (24, 44). When the transistor (71, 91) is OFF, this clamps the buried layer voltage and substantially prevents noise coupling thereto. When the drain-source voltage VDS exceeds the switch's (80, 80′) threshold voltage Vt, it turns OFF, allowing the buried layer (102, 142, 172, 202) to float, and thereby resume normal transistor action without degrading the breakdown voltage or ON-resistance. In a preferred embodiment, a normally-ON lateral JFET (801, 801′, 801-1, 801-2, 801-3) conveniently provides this switching function. The lateral JFET (801-3) can be included in the device (70, 70′, 90, 90′) by mask changes without adding or customizing any process steps, thereby providing the improved noise resistance without significant increase in manufacturing cost. The improvement applies to both P (90-1) and N channel (70-1, 70-2, 70-3) transistors and is particularly useful for LDMOS devices.
摘要翻译： 使用浮置掩埋层的晶体管（21,41）可能易于与浮动掩埋层的噪声耦合。 在IGFETS中，通过提供耦合埋层（102,142,172,202）和IGFET源（22,42）或漏极（24,44）的常开开关（80,80'）来减少或消除这种情况。 当晶体管（71,91）为OFF时，这夹着埋层电压并且基本上防止与其耦合的噪声。 当漏极 - 源极电压V DS超过开关（80,80'）阈值电压Vt时，它变为OFF，允许埋层（102,142,172,202）浮起，从而恢复正常的晶体管作用而不降低击穿 电压或导通电阻。 在优选实施例中，正向导通的横向JFET（801,801'，801-1,801-2,801-3）方便地提供该开关功能。 横向JFET（801-3）可以通过掩模改变而被包括在设备（70,70'，90,90'）中，而不需要添加或定制任何工艺步骤，从而提供改进的抗噪声性，而不会显着增加制造成本。 该改进适用于P（90-1）和N通道（70-1,70-2,70-3）晶体管，并且对于LDMOS器件特别有用。
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公开(公告)号：US09601638B2
公开(公告)日：2017-03-21
申请号：US13276875
申请日：2011-10-19
申请人： Jenn Hwa Huang , Weixiao Huang
发明人： Jenn Hwa Huang , Weixiao Huang
IPC分类号： H01L21/8234 , H01L29/812 , H01L29/66 , H01L29/20 , H01L21/265 , H01L29/51
CPC分类号： H01L29/1083 , H01L21/26506 , H01L21/2654 , H01L21/266 , H01L21/30612 , H01L21/308 , H01L23/291 , H01L23/3171 , H01L29/1037 , H01L29/2003 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/66863 , H01L29/812
摘要： A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11, 13) with one or more device mesas (41) in which isolation regions (92, 93) are formed using an implant mask (81) to implant ions (91) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode (111) from contacting the peripheral edge and sidewalls of the mesa structures.
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公开(公告)号：US20130099324A1
公开(公告)日：2013-04-25
申请号：US13276875
申请日：2011-10-19
申请人： Jenn Hwa Huang , Weixiao Huang
发明人： Jenn Hwa Huang , Weixiao Huang
IPC分类号： H01L29/78 , H01L21/337
CPC分类号： H01L29/1083 , H01L21/26506 , H01L21/2654 , H01L21/266 , H01L21/30612 , H01L21/308 , H01L23/291 , H01L23/3171 , H01L29/1037 , H01L29/2003 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/66863 , H01L29/812
摘要： A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11, 13) with one or more device mesas (41) in which isolation regions (92, 93) are formed using an implant mask (81) to implant ions (91) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode (111) from contacting the peripheral edge and sidewalls of the mesa structures.
摘要翻译： 提供了一种低泄漏电流开关装置（110），其包括具有一个或多个器件台面（41）的GaN-on-Si衬底（11,13），其中使用植入掩模形成隔离区域（92,93） 81）将离子（91）注入到通过注入掩模暴露的台面结构的每个升高的表面周围的台面侧壁的上部和周边区域中，从而防止随后形成的栅电极（111）与周边边缘接触 台面结构的侧壁。
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公开(公告)号：US08653558B2
公开(公告)日：2014-02-18
申请号：US13273622
申请日：2011-10-14
申请人： Bruce M. Green , Jenn Hwa Huang , Weixiao Huang
发明人： Bruce M. Green , Jenn Hwa Huang , Weixiao Huang
IPC分类号： H01L29/66 , H01L21/337
CPC分类号： H01L29/7787 , H01L21/28264 , H01L29/2003 , H01L29/513 , H01L29/517 , H01L29/66462
摘要： In some embodiments, a metal insulator semiconductor heterostructure field effect transistor (MISHFET) is disclosed that has a source, a drain, an insulation layer, a gate dielectric, and a gate. The source and drain are on opposing sides of a channel region of a channel layer. The channel region is an upper portion of the channel layer. The channel layer comprises gallium nitride. The insulation layer is over the channel layer and has a first portion and a second portion. The first portion is nearer the drain than the source and has a first thickness. The second portion is nearer the source than drain and has the first thickness. The insulation layer has an opening through the insulation layer. The opening is between the first portion and the second portion.
摘要翻译： 在一些实施例中，公开了具有源极，漏极，绝缘层，栅极电介质和栅极的金属绝缘体半导体异质结构场效应晶体管（MISHFET）。 源极和漏极在沟道层的沟道区域的相对侧上。 沟道区是沟道层的上部。 沟道层包括氮化镓。 绝缘层在沟道层上方并具有第一部分和第二部分。 第一部分比源极更靠近漏极并具有第一厚度。 第二部分比排水源更靠近源头并具有第一厚度。 绝缘层具有穿过绝缘层的开口。 开口位于第一部分和第二部分之间。
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公开(公告)号：US20130092947A1
公开(公告)日：2013-04-18
申请号：US13273622
申请日：2011-10-14
申请人： BRUCE M. GREEN , Jenn Hwa Huang , Weixiao Huang
发明人： BRUCE M. GREEN , Jenn Hwa Huang , Weixiao Huang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7787 , H01L21/28264 , H01L29/2003 , H01L29/513 , H01L29/517 , H01L29/66462
摘要： In some embodiments, a metal insulator semiconductor heterostructure field effect transistor (MISHFET) is disclosed that has a source, a drain, an insulation layer, a gate dielectric, and a gate. The source and drain are on opposing sides of a channel region of a channel layer. The channel region is an upper portion of the channel layer. The channel layer comprises gallium nitride. The insulation layer is over the channel layer and has a first portion and a second portion. The first portion is nearer the drain than the source and has a first thickness. The second portion is nearer the source than drain and has the first thickness. The insulation layer has an opening through the insulation layer. The opening is between the first portion and the second portion.
摘要翻译： 在一些实施例中，公开了具有源极，漏极，绝缘层，栅极电介质和栅极的金属绝缘体半导体异质结构场效应晶体管（MISHFET）。 源极和漏极在沟道层的沟道区域的相对侧上。 沟道区是沟道层的上部。 沟道层包括氮化镓。 绝缘层在沟道层上方并具有第一部分和第二部分。 第一部分比源极更靠近漏极并具有第一厚度。 第二部分比排水源更靠近源头并具有第一厚度。 绝缘层具有穿过绝缘层的开口。 开口位于第一部分和第二部分之间。
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