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公开(公告)号：US08338872B2
公开(公告)日：2012-12-25
申请号：US12750166
申请日：2010-03-30
CPC分类号： H01L27/0705 , H01L27/088 , H01L27/098 , H01L29/0653 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69′) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94′) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94′) may be external to the transistor (69, 69′), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69′-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.
摘要翻译： 使用浮动掩埋层（BL）（72）的晶体管（21,41）可以显示出显着小于（BVdss）DC的瞬态击穿电压（BVdss）TR。 发现这是因为浮动BL（72）不能快速跟随施加的瞬态，导致装置内的局部电场暂时超过雪崩状况。 通过包括将浮动BL（72）耦合到无论哪个高侧端子（...）的电荷泵电容（94,94'），可以将这种晶体管（69.69'）的（BVdss）TR提高到等于或超过（BVdss） 28，47）接收瞬态。 电荷泵电容（94,94'）可以在晶体管（69,69'）的外部，可以形成在器件表面（71）上，或者可以形成在晶体管（69-3,69' 3）使用分离延伸到BL（72）的直流隔离沉降片区域（86,88）的电介质深沟槽隔离壁（100）。 该改进对于LDMOS器件特别有用。
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公开(公告)号：US20110241092A1
公开(公告)日：2011-10-06
申请号：US12750166
申请日：2010-03-30
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0705 , H01L27/088 , H01L27/098 , H01L29/0653 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69′) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94′) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94′) may be external to the transistor (69, 69′), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69′-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.
摘要翻译： 使用浮动掩埋层（BL）（72）的晶体管（21,41）可以显示出显着小于（BVdss）DC的瞬态击穿电压（BVdss）TR。 发现这是因为浮动BL（72）不能快速跟随施加的瞬态，导致装置内的局部电场暂时超过雪崩状况。 通过包括将浮动BL（72）耦合到无论哪个高侧端子（...）的电荷泵电容（94,94'），可以将这种晶体管（69.69'）的（BVdss）TR提高到等于或超过（BVdss） 28，47）接收瞬态。 电荷泵电容（94,94'）可以在晶体管（69,69'）的外部，可以形成在器件表面（71）上，或者可以形成在晶体管（69-3,69' 3）使用分离延伸到BL（72）的直流隔离沉降片区域（86,88）的电介质深沟槽隔离壁（100）。 该改进对于LDMOS器件特别有用。
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公开(公告)号：US08193585B2
公开(公告)日：2012-06-05
申请号：US12608586
申请日：2009-10-29
IPC分类号： H01L29/66
CPC分类号： H01L29/7835 , H01L29/063 , H01L29/0653 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： Methods and apparatus are provided for fabricating a semiconductor device structure. The semiconductor device structure comprises a buried region having a first conductivity type, a first region having a second conductivity type overlying the buried region, a source region having the first conductivity type overlying the first region, and a drain region having the first conductivity type overlying the first region. The semiconductor device structure further comprises a second region having the first conductivity type overlying the buried region, the second region abutting the buried region to form an electrical contact with the buried region, and a first resistance configured electrically in series with the second region and the buried region. The combined series resistance of the first resistance and the second region is greater than a resistance of the buried region.
摘要翻译： 提供了用于制造半导体器件结构的方法和装置。 半导体器件结构包括具有第一导电类型的掩埋区域，覆盖掩埋区域的具有第二导电类型的第一区域，覆盖第一区域的具有第一导电类型的源极区域和覆盖第一导电类型的漏极区域 第一个地区。 所述半导体器件结构还包括具有覆盖所述掩埋区域的所述第一导电类型的第二区域，所述第二区域邻接所述掩埋区域以与所述掩埋区域形成电接触，以及与所述第二区域串联构造的第一电阻和 埋地区 第一电阻和第二区域的组合串联电阻大于埋入区域的电阻。
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公开(公告)号：US20110101425A1
公开(公告)日：2011-05-05
申请号：US12608586
申请日：2009-10-29
IPC分类号： H01L29/78 , H01L21/8232
CPC分类号： H01L29/7835 , H01L29/063 , H01L29/0653 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： Methods and apparatus are provided for fabricating a semiconductor device structure. The semiconductor device structure comprises a buried region having a first conductivity type, a first region having a second conductivity type overlying the buried region, a source region having the first conductivity type overlying the first region, and a drain region having the first conductivity type overlying the first region. The semiconductor device structure further comprises a second region having the first conductivity type overlying the buried region, the second region abutting the buried region to form an electrical contact with the buried region, and a first resistance configured electrically in series with the second region and the buried region. The combined series resistance of the first resistance and the second region is greater than a resistance of the buried region.
摘要翻译： 提供了用于制造半导体器件结构的方法和装置。 半导体器件结构包括具有第一导电类型的掩埋区域，覆盖掩埋区域的具有第二导电类型的第一区域，覆盖第一区域的具有第一导电类型的源极区域和覆盖第一导电类型的漏极区域 第一个地区。 所述半导体器件结构还包括具有覆盖所述掩埋区域的所述第一导电类型的第二区域，所述第二区域邻接所述掩埋区域以与所述掩埋区域形成电接触，以及与所述第二区域串联构造的第一电阻和 埋地区。 第一电阻和第二区域的组合串联电阻大于埋入区域的电阻。
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公开(公告)号：US08384184B2
公开(公告)日：2013-02-26
申请号：US12882899
申请日：2010-09-15
IPC分类号： H01L29/78
CPC分类号： H01L29/66681 , H01L21/02107 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.
摘要翻译： 这里介绍一种半导体器件和相关的制造工艺。 该器件包括支撑衬底，覆盖在支撑衬底上的掩埋氧化物层，位于掩埋氧化物层上方并具有第一导电类型的第一半导体区域。 该器件还包括第二，第三，第四和第五半导体区域。 第二半导体区域位于第一半导体区域的上方，具有第二导电型。 第三半导体区域位于第二半导体区域的上方，具有第一导电型。 第四半导体区域位于第三半导体区域的上方，具有第二导电型。 第五半导体区域延伸穿过第四半导体区域和第三半导体区域到第二半导体区域，并且具有第二导电类型。
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公开(公告)号：US20120061758A1
公开(公告)日：2012-03-15
申请号：US12882899
申请日：2010-09-15
CPC分类号： H01L29/66681 , H01L21/02107 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.
摘要翻译： 这里介绍一种半导体器件和相关的制造工艺。 该器件包括支撑衬底，覆盖在支撑衬底上的掩埋氧化物层，位于掩埋氧化物层上方并具有第一导电类型的第一半导体区域。 该器件还包括第二，第三，第四和第五半导体区域。 第二半导体区域位于第一半导体区域的上方，具有第二导电型。 第三半导体区域位于第二半导体区域的上方，具有第一导电型。 第四半导体区域位于第三半导体区域的上方，具有第二导电型。 第五半导体区域延伸穿过第四半导体区域和第三半导体区域到第二半导体区域，并且具有第二导电类型。
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7.发明申请LATERALLY DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR HAVING A REDUCED SURFACE FIELD STRUCTURE AND METHOD THEREFOR 有权具有减少表面的双向扩散金属氧化物半导体晶体管现场结构及其方法公开(公告)号：US20110309442A1
公开(公告)日：2011-12-22
申请号：US12817805
申请日：2010-06-17
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/063 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66689 , H01L29/7824
摘要： An LDMOS transistor includes a substrate of semiconductor material, an insulator layer overlying the substrate, a semiconductor layer overlying the insulator layer, a RESURF region, and a gate. The semiconductor layer includes a first conductivity type well region, a second conductivity type source region in contact with the first conductivity type well region, a second conductivity type drain region. The RESURF region includes at least one first conductivity type material portion, and at least one portion of the at least one first conductivity type material portion electrically coupled to the first conductivity type well region. A semiconductor material having a second conductivity type is located below the RESURF region. The second conductivity type semiconductor material is also located over a part of the RESURF region. The gate is located over the first conductivity type well region and over the RESURF region.
摘要翻译： LDMOS晶体管包括半导体材料的衬底，覆盖衬底的绝缘体层，覆盖绝缘体层的半导体层，RESURF区域和栅极。 半导体层包括第一导电类型阱区，与第一导电类型阱区接触的第二导电类型源区，第二导电类型漏区。 RESURF区域包括至少一个第一导电类型的材料部分，以及电耦合到第一导电类型阱区的至少一个第一导电型材料部分的至少一部分。 具有第二导电类型的半导体材料位于RESURF区域的下方。 第二导电型半导体材料也位于RESURF区域的一部分上。 栅极位于第一导电类型阱区域和RESURF区域之上。
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8.发明授权Methods of making laterally double diffused metal oxide semiconductor transistors having a reduced surface field structure 有权制造具有减小的表面场结构的横向双扩散金属氧化物半导体晶体管的方法公开(公告)号：US08623732B2
公开(公告)日：2014-01-07
申请号：US12817805
申请日：2010-06-17
IPC分类号： H01L21/331 , H01L29/66
CPC分类号： H01L29/7816 , H01L29/063 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66689 , H01L29/7824
摘要： An LDMOS transistor includes a substrate of semiconductor material, an insulator layer overlying the substrate, a semiconductor layer overlying the insulator layer, a RESURF region, and a gate. The semiconductor layer includes a first conductivity type well region, a second conductivity type source region in contact with the first conductivity type well region, a second conductivity type drain region. The RESURF region includes at least one first conductivity type material portion, and at least one portion of the at least one first conductivity type material portion electrically coupled to the first conductivity type well region. A semiconductor material having a second conductivity type is located below the RESURF region. The second conductivity type semiconductor material is also located over a part of the RESURF region. The gate is located over the first conductivity type well region and over the RESURF region.
摘要翻译： LDMOS晶体管包括半导体材料的衬底，覆盖衬底的绝缘体层，覆盖绝缘体层的半导体层，RESURF区域和栅极。 半导体层包括第一导电类型阱区，与第一导电类型阱区接触的第二导电类型源区，第二导电类型漏区。 RESURF区域包括至少一个第一导电类型的材料部分，以及电耦合到第一导电类型阱区的至少一个第一导电型材料部分的至少一部分。 具有第二导电类型的半导体材料位于RESURF区域的下方。 第二导电型半导体材料也位于RESURF区域的一部分上。 栅极位于第一导电类型阱区域和RESURF区域之上。
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公开(公告)号：US08344472B2
公开(公告)日：2013-01-01
申请号：US12750151
申请日：2010-03-30
申请人： Vishnu K. Khemka , Tahir A. Khan , Weixiao Huang , Ronghua Zhu
发明人： Vishnu K. Khemka , Tahir A. Khan , Weixiao Huang , Ronghua Zhu
IPC分类号： H01L29/66
CPC分类号： H01L27/098 , H01L27/0705 , H01L27/085 , H01L27/088 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers may be susceptible to noise coupling into the floating buried layers. In IGFETS this is reduced or eliminated by providing a normally-ON switch (80, 80′) coupling the buried layer (102, 142, 172, 202) and the IGFET source (22, 42) or drain (24, 44). When the transistor (71, 91) is OFF, this clamps the buried layer voltage and substantially prevents noise coupling thereto. When the drain-source voltage VDS exceeds the switch's (80, 80′) threshold voltage Vt, it turns OFF, allowing the buried layer (102, 142, 172, 202) to float, and thereby resume normal transistor action without degrading the breakdown voltage or ON-resistance. In a preferred embodiment, a normally-ON lateral JFET (801, 801′, 801-1, 801-2, 801-3) conveniently provides this switching function. The lateral JFET (801-3) can be included in the device (70, 70′, 90, 90′) by mask changes without adding or customizing any process steps, thereby providing the improved noise resistance without significant increase in manufacturing cost. The improvement applies to both P (90-1) and N channel (70-1, 70-2, 70-3) transistors and is particularly useful for LDMOS devices.
摘要翻译： 使用浮置掩埋层的晶体管（21,41）可能易于与浮动掩埋层的噪声耦合。 在IGFETS中，通过提供耦合埋层（102,142,172,202）和IGFET源（22,42）或漏极（24,44）的常开开关（80,80'）来减少或消除这种情况。 当晶体管（71,91）为OFF时，这夹着埋层电压并且基本上防止与其耦合的噪声。 当漏极 - 源极电压V DS超过开关（80,80'）阈值电压Vt时，它变为OFF，允许埋层（102,142,172,202）浮起，从而恢复正常的晶体管作用而不降低击穿 电压或导通电阻。 在优选实施例中，正向导通的横向JFET（801,801'，801-1,801-2,801-3）方便地提供该开关功能。 横向JFET（801-3）可以通过掩模改变而被包括在设备（70,70'，90,90'）中，而不需要添加或定制任何工艺步骤，从而提供改进的抗噪声性，而不会显着增加制造成本。 该改进适用于P（90-1）和N通道（70-1,70-2,70-3）晶体管，并且对于LDMOS器件特别有用。
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公开(公告)号：US20110241083A1
公开(公告)日：2011-10-06
申请号：US12750151
申请日：2010-03-30
申请人： Vishnu K. Khemka , Tahir A. Khan , Weixiao Huang , Ronghua Zhu
发明人： Vishnu K. Khemka , Tahir A. Khan , Weixiao Huang , Ronghua Zhu
IPC分类号： H01L27/085 , H01L21/8232
CPC分类号： H01L27/098 , H01L27/0705 , H01L27/085 , H01L27/088 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers may be susceptible to noise coupling into the floating buried layers. In IGFETS this is reduced or eliminated by providing a normally-ON switch (80, 80′) coupling the buried layer (102, 142, 172, 202) and the IGFET source (22, 42) or drain (24, 44). When the transistor (71, 91) is OFF, this clamps the buried layer voltage and substantially prevents noise coupling thereto. When the drain-source voltage VDS exceeds the switch's (80, 80′) threshold voltage Vt, it turns OFF, allowing the buried layer (102, 142, 172, 202) to float, and thereby resume normal transistor action without degrading the breakdown voltage or ON-resistance. In a preferred embodiment, a normally-ON lateral JFET (801, 801′, 801-1, 801-2, 801-3) conveniently provides this switching function. The lateral JFET (801-3) can be included in the device (70, 70′, 90, 90′) by mask changes without adding or customizing any process steps, thereby providing the improved noise resistance without significant increase in manufacturing cost. The improvement applies to both P (90-1) and N channel (70-1, 70-2, 70-3) transistors and is particularly useful for LDMOS devices.
摘要翻译： 使用浮置掩埋层的晶体管（21,41）可能易于与浮动掩埋层的噪声耦合。 在IGFETS中，通过提供耦合埋层（102,142,172,202）和IGFET源（22,42）或漏极（24,44）的常开开关（80,80'）来减少或消除这种情况。 当晶体管（71,91）为OFF时，这夹着埋层电压并且基本上防止与其耦合的噪声。 当漏极 - 源极电压V DS超过开关（80,80'）阈值电压Vt时，它变为OFF，允许埋层（102,142,172,202）浮起，从而恢复正常的晶体管作用而不降低击穿 电压或导通电阻。 在优选实施例中，正向导通的横向JFET（801,801'，801-1,801-2,801-3）方便地提供该开关功能。 横向JFET（801-3）可以通过掩模改变而被包括在设备（70,70'，90,90'）中，而不需要添加或定制任何工艺步骤，从而提供改进的抗噪声性，而不会显着增加制造成本。 该改进适用于P（90-1）和N通道（70-1,70-2,70-3）晶体管，并且对于LDMOS器件特别有用。
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