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公开(公告)号：US08193585B2
公开(公告)日：2012-06-05
申请号：US12608586
申请日：2009-10-29
IPC分类号： H01L29/66
CPC分类号： H01L29/7835 , H01L29/063 , H01L29/0653 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： Methods and apparatus are provided for fabricating a semiconductor device structure. The semiconductor device structure comprises a buried region having a first conductivity type, a first region having a second conductivity type overlying the buried region, a source region having the first conductivity type overlying the first region, and a drain region having the first conductivity type overlying the first region. The semiconductor device structure further comprises a second region having the first conductivity type overlying the buried region, the second region abutting the buried region to form an electrical contact with the buried region, and a first resistance configured electrically in series with the second region and the buried region. The combined series resistance of the first resistance and the second region is greater than a resistance of the buried region.
摘要翻译： 提供了用于制造半导体器件结构的方法和装置。 半导体器件结构包括具有第一导电类型的掩埋区域，覆盖掩埋区域的具有第二导电类型的第一区域，覆盖第一区域的具有第一导电类型的源极区域和覆盖第一导电类型的漏极区域 第一个地区。 所述半导体器件结构还包括具有覆盖所述掩埋区域的所述第一导电类型的第二区域，所述第二区域邻接所述掩埋区域以与所述掩埋区域形成电接触，以及与所述第二区域串联构造的第一电阻和 埋地区 第一电阻和第二区域的组合串联电阻大于埋入区域的电阻。
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公开(公告)号：US20110101425A1
公开(公告)日：2011-05-05
申请号：US12608586
申请日：2009-10-29
IPC分类号： H01L29/78 , H01L21/8232
CPC分类号： H01L29/7835 , H01L29/063 , H01L29/0653 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： Methods and apparatus are provided for fabricating a semiconductor device structure. The semiconductor device structure comprises a buried region having a first conductivity type, a first region having a second conductivity type overlying the buried region, a source region having the first conductivity type overlying the first region, and a drain region having the first conductivity type overlying the first region. The semiconductor device structure further comprises a second region having the first conductivity type overlying the buried region, the second region abutting the buried region to form an electrical contact with the buried region, and a first resistance configured electrically in series with the second region and the buried region. The combined series resistance of the first resistance and the second region is greater than a resistance of the buried region.
摘要翻译： 提供了用于制造半导体器件结构的方法和装置。 半导体器件结构包括具有第一导电类型的掩埋区域，覆盖掩埋区域的具有第二导电类型的第一区域，覆盖第一区域的具有第一导电类型的源极区域和覆盖第一导电类型的漏极区域 第一个地区。 所述半导体器件结构还包括具有覆盖所述掩埋区域的所述第一导电类型的第二区域，所述第二区域邻接所述掩埋区域以与所述掩埋区域形成电接触，以及与所述第二区域串联构造的第一电阻和 埋地区。 第一电阻和第二区域的组合串联电阻大于埋入区域的电阻。
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公开(公告)号：US08338872B2
公开(公告)日：2012-12-25
申请号：US12750166
申请日：2010-03-30
CPC分类号： H01L27/0705 , H01L27/088 , H01L27/098 , H01L29/0653 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69′) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94′) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94′) may be external to the transistor (69, 69′), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69′-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.
摘要翻译： 使用浮动掩埋层（BL）（72）的晶体管（21,41）可以显示出显着小于（BVdss）DC的瞬态击穿电压（BVdss）TR。 发现这是因为浮动BL（72）不能快速跟随施加的瞬态，导致装置内的局部电场暂时超过雪崩状况。 通过包括将浮动BL（72）耦合到无论哪个高侧端子（...）的电荷泵电容（94,94'），可以将这种晶体管（69.69'）的（BVdss）TR提高到等于或超过（BVdss） 28，47）接收瞬态。 电荷泵电容（94,94'）可以在晶体管（69,69'）的外部，可以形成在器件表面（71）上，或者可以形成在晶体管（69-3,69' 3）使用分离延伸到BL（72）的直流隔离沉降片区域（86,88）的电介质深沟槽隔离壁（100）。 该改进对于LDMOS器件特别有用。
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公开(公告)号：US20110241092A1
公开(公告)日：2011-10-06
申请号：US12750166
申请日：2010-03-30
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0705 , H01L27/088 , H01L27/098 , H01L29/0653 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69′) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94′) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94′) may be external to the transistor (69, 69′), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69′-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.
摘要翻译： 使用浮动掩埋层（BL）（72）的晶体管（21,41）可以显示出显着小于（BVdss）DC的瞬态击穿电压（BVdss）TR。 发现这是因为浮动BL（72）不能快速跟随施加的瞬态，导致装置内的局部电场暂时超过雪崩状况。 通过包括将浮动BL（72）耦合到无论哪个高侧端子（...）的电荷泵电容（94,94'），可以将这种晶体管（69.69'）的（BVdss）TR提高到等于或超过（BVdss） 28，47）接收瞬态。 电荷泵电容（94,94'）可以在晶体管（69,69'）的外部，可以形成在器件表面（71）上，或者可以形成在晶体管（69-3,69' 3）使用分离延伸到BL（72）的直流隔离沉降片区域（86,88）的电介质深沟槽隔离壁（100）。 该改进对于LDMOS器件特别有用。
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公开(公告)号：US08384184B2
公开(公告)日：2013-02-26
申请号：US12882899
申请日：2010-09-15
IPC分类号： H01L29/78
CPC分类号： H01L29/66681 , H01L21/02107 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.
摘要翻译： 这里介绍一种半导体器件和相关的制造工艺。 该器件包括支撑衬底，覆盖在支撑衬底上的掩埋氧化物层，位于掩埋氧化物层上方并具有第一导电类型的第一半导体区域。 该器件还包括第二，第三，第四和第五半导体区域。 第二半导体区域位于第一半导体区域的上方，具有第二导电型。 第三半导体区域位于第二半导体区域的上方，具有第一导电型。 第四半导体区域位于第三半导体区域的上方，具有第二导电型。 第五半导体区域延伸穿过第四半导体区域和第三半导体区域到第二半导体区域，并且具有第二导电类型。
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6.发明授权Methods of making laterally double diffused metal oxide semiconductor transistors having a reduced surface field structure 有权制造具有减小的表面场结构的横向双扩散金属氧化物半导体晶体管的方法公开(公告)号：US08623732B2
公开(公告)日：2014-01-07
申请号：US12817805
申请日：2010-06-17
IPC分类号： H01L21/331 , H01L29/66
CPC分类号： H01L29/7816 , H01L29/063 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66689 , H01L29/7824
摘要： An LDMOS transistor includes a substrate of semiconductor material, an insulator layer overlying the substrate, a semiconductor layer overlying the insulator layer, a RESURF region, and a gate. The semiconductor layer includes a first conductivity type well region, a second conductivity type source region in contact with the first conductivity type well region, a second conductivity type drain region. The RESURF region includes at least one first conductivity type material portion, and at least one portion of the at least one first conductivity type material portion electrically coupled to the first conductivity type well region. A semiconductor material having a second conductivity type is located below the RESURF region. The second conductivity type semiconductor material is also located over a part of the RESURF region. The gate is located over the first conductivity type well region and over the RESURF region.
摘要翻译： LDMOS晶体管包括半导体材料的衬底，覆盖衬底的绝缘体层，覆盖绝缘体层的半导体层，RESURF区域和栅极。 半导体层包括第一导电类型阱区，与第一导电类型阱区接触的第二导电类型源区，第二导电类型漏区。 RESURF区域包括至少一个第一导电类型的材料部分，以及电耦合到第一导电类型阱区的至少一个第一导电型材料部分的至少一部分。 具有第二导电类型的半导体材料位于RESURF区域的下方。 第二导电型半导体材料也位于RESURF区域的一部分上。 栅极位于第一导电类型阱区域和RESURF区域之上。
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公开(公告)号：US20120061758A1
公开(公告)日：2012-03-15
申请号：US12882899
申请日：2010-09-15
CPC分类号： H01L29/66681 , H01L21/02107 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device and a related fabrication process are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.
摘要翻译： 这里介绍一种半导体器件和相关的制造工艺。 该器件包括支撑衬底，覆盖在支撑衬底上的掩埋氧化物层，位于掩埋氧化物层上方并具有第一导电类型的第一半导体区域。 该器件还包括第二，第三，第四和第五半导体区域。 第二半导体区域位于第一半导体区域的上方，具有第二导电型。 第三半导体区域位于第二半导体区域的上方，具有第一导电型。 第四半导体区域位于第三半导体区域的上方，具有第二导电型。 第五半导体区域延伸穿过第四半导体区域和第三半导体区域到第二半导体区域，并且具有第二导电类型。
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8.发明申请LATERALLY DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR HAVING A REDUCED SURFACE FIELD STRUCTURE AND METHOD THEREFOR 有权具有减少表面的双向扩散金属氧化物半导体晶体管现场结构及其方法公开(公告)号：US20110309442A1
公开(公告)日：2011-12-22
申请号：US12817805
申请日：2010-06-17
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/063 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66689 , H01L29/7824
摘要： An LDMOS transistor includes a substrate of semiconductor material, an insulator layer overlying the substrate, a semiconductor layer overlying the insulator layer, a RESURF region, and a gate. The semiconductor layer includes a first conductivity type well region, a second conductivity type source region in contact with the first conductivity type well region, a second conductivity type drain region. The RESURF region includes at least one first conductivity type material portion, and at least one portion of the at least one first conductivity type material portion electrically coupled to the first conductivity type well region. A semiconductor material having a second conductivity type is located below the RESURF region. The second conductivity type semiconductor material is also located over a part of the RESURF region. The gate is located over the first conductivity type well region and over the RESURF region.
摘要翻译： LDMOS晶体管包括半导体材料的衬底，覆盖衬底的绝缘体层，覆盖绝缘体层的半导体层，RESURF区域和栅极。 半导体层包括第一导电类型阱区，与第一导电类型阱区接触的第二导电类型源区，第二导电类型漏区。 RESURF区域包括至少一个第一导电类型的材料部分，以及电耦合到第一导电类型阱区的至少一个第一导电型材料部分的至少一部分。 具有第二导电类型的半导体材料位于RESURF区域的下方。 第二导电型半导体材料也位于RESURF区域的一部分上。 栅极位于第一导电类型阱区域和RESURF区域之上。
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公开(公告)号：US07608908B1
公开(公告)日：2009-10-27
申请号：US12125613
申请日：2008-05-22
申请人： Vishnu Khemka , Amitava Bose , Michael C. Butner , Bernhard H. Grote , Tahir A. Khan , Shifeng Shen , Ronghua Zhu
发明人： Vishnu Khemka , Amitava Bose , Michael C. Butner , Bernhard H. Grote , Tahir A. Khan , Shifeng Shen , Ronghua Zhu
IPC分类号： H01L29/00 , H01L29/167
CPC分类号： H01L21/76264
摘要： Higher voltage device isolation structures (40, 60, 70, 80, 90, 90′) are provided for semiconductor integrated circuits having strongly doped buried layers (24, 24″). One or more dielectric lined deep isolation trenches (27, 27′, 27″, 27′″) separates adjacent device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912). Electrical breakdown (BVdss) between the device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912) and the oppositely doped substrate (22, 22″) is found to occur preferentially where the buried layer (24, 24″) intersects the dielectric sidewalls (273, 274; 273′, 274′; 273″, 274″) of the trench (27, 27′, 27″, 27′″). The breakdown voltage (BVdss) is increased by providing a more lightly doped region (42, 42″, 62, 72, 82) of the same conductivity type as the buried layer (24, 24″), underlying the buried layer (24, 24″) at the trench sidewalls (273, 274; 273′, 274′; 273″, 274″). The more lightly doped region's (42, 42″, 62, 72, 82) dopant concentration is desirably 1E4 to 2E2 times less than the buried layer (24, 24″) and it extends substantially entirely beneath the buried layer (24, 24″) or to a distance (724, 824) extending about 0.5 to 2.0 micro-meters from the trench sidewall (273, 274; 273′, 274′; 273″, 274″). In a preferred embodiment, the trench (27, 27′) is split into two portions (271, 272; 271′, 272′) with the semiconductor therein (475, 675, 775, 875) ohmically coupled to the substrate (22).
摘要翻译： 为具有强掺杂掩埋层（24,24“）的半导体集成电路提供更高电压器件隔离结构（40,60,70,80,90,90'）。 一个或多个电介质衬里的深隔离沟槽（27,27'，27“，27”'）分隔相邻的器件区域（411,412; 611,612; 711,712; 811,812; 911,912）。 发现器件区域（411,412; 611,612; 711,712; 811,812; 911,912）和相对掺杂的衬底（22,22“）之间的电击穿（BVdss）优先发生在埋置 层（24,24“）与沟槽（27,27'，27”，27“'）的电介质侧壁（273,274; 273'，274'; 273”，274“）相交。 通过提供与掩埋层下面的掩埋层（24,24“）相同的导电类型的更轻掺杂区域（42,42”，62,72,82）来增加击穿电压（BVdss） （273,274; 273'，274'; 273“，”274“）上。 掺杂浓度越高的掺杂区越好，比掩埋层（24,24“）要小1〜4埃，比埋入层（24，24”）大致全部下降， 距离沟槽侧壁（273,274; 273'，274'; 273“，”274“）延伸约0.5至2.0微米的距离（724,824）。 在优选实施例中，沟槽（27,27'）被分成两部分（271,272; 271'，272'），其中半导体在其中欧姆耦合到衬底（22），其中（475,675,775,875） 。
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公开(公告)号：US08922227B2
公开(公告)日：2014-12-30
申请号：US13043075
申请日：2011-03-08
申请人： Chad S. Dawson , Bernhard H. Grote , Woo Tae Park
发明人： Chad S. Dawson , Bernhard H. Grote , Woo Tae Park
CPC分类号： G01R29/24
摘要： Systems and methods are provided for detecting surface charge on a semiconductor substrate having a sensing arrangement formed thereon. An exemplary sensing system includes the semiconductor substrate having the sensing arrangement formed thereon, and a module coupled to the sensing arrangement. The module obtains a first voltage output from the sensing arrangement when a first voltage is applied to the semiconductor substrate, obtains a second voltage output from the sensing arrangement when a second voltage is applied to the semiconductor substrate, and detects electric charge on the surface of the semiconductor substrate based on a difference between the first voltage output and the second voltage output.
摘要翻译： 提供了用于检测在其上形成有感测装置的半导体衬底上的表面电荷的系统和方法。 示例性感测系统包括其上形成有感测装置的半导体衬底和耦合到感测装置的模块。 当向半导体衬底施加第一电压时，模块获得从感测装置输出的第一电压，当向半导体衬底施加第二电压时获得从感测装置输出的第二电压，并且检测表面上的电荷 基于第一电压输出和第二电压输出之间的差的半导体衬底。
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