公开(公告)号：US20130229882A1

公开(公告)日：2013-09-05

申请号：US13870598

申请日：2013-04-25

申请人： Walid M. Hafez ,  Anisur Rahman ,  Chia-Hong Jan

发明人： Walid M. Hafez ,  Anisur Rahman ,  Chia-Hong Jan

IPC分类号： G11C7/00 ,  H03K19/173

CPC分类号： G11C7/00 ,  G11C17/16 ,  G11C17/18 ,  H03K19/173

摘要： Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments.

摘要翻译： 公开了用于实现利用高k /金属栅极n型或p型金属氧化物半导体（NMOS或PMOS）晶体管的偏置温度不稳定性（BTI）效应的非易失性存储器的技术和电路。 例如，存储器或可编程逻辑电路的编程位单元表现出由用于编程位单元的应用编程偏置产生的阈值电压偏移。 在一些情况下，施加第一编程偏置使得器件具有第一状态，并且施加第二编程偏置使得器件具有与第一状态不同的第二状态。 可以通过施加相反的极性应力来擦除编程的位单元，并通过多个周期重新编程。 根据一些实施例，位单元配置可以与列/行选择电路和/或读出电路结合使用。

公开(公告)号：US08101471B2

公开(公告)日：2012-01-24

申请号：US12319104

申请日：2008-12-30

申请人： Walid M. Hafez ,  Chia-Hong Jan ,  Jie-Feng Lin ,  Chetan Prasad ,  Sangwoo Pae ,  Zhanping Chen ,  Anisur Rahman

发明人： Walid M. Hafez ,  Chia-Hong Jan ,  Jie-Feng Lin ,  Chetan Prasad ,  Sangwoo Pae ,  Zhanping Chen ,  Anisur Rahman

IPC分类号： H01L21/82

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

摘要： A programmable anti-fuse element includes a substrate (224), an N-well (426) in the substrate, an electrically insulating layer (427) over the N-well, and a gate electrode (430) over the electrically insulating layer. The gate electrode has n-type doping so that the N-well is able to substantially contain within its boundaries a current generated following a programming event of the programmable anti-fuse element. In the same or another embodiment, a twice-programmable fuse element (100) includes a metal gate fuse (110) and an oxide anti-fuse (120) such as the programmable anti-fuse element just described.

摘要翻译： 可编程抗熔丝元件包括衬底（224），衬底中的N阱（426），在N阱上的电绝缘层（427）以及电绝缘层上的栅电极（430）。 栅电极具有n型掺杂，使得N阱能够在其边界内基本上包含在可编程反熔丝元件的编程事件之后产生的电流。 在相同或另一个实施例中，两次可编程熔丝元件（100）包括金属栅极熔丝（110）和氧化物反熔丝（120），例如刚刚描述的可编程反熔丝元件。

公开(公告)号：US20120163103A1

公开(公告)日：2012-06-28

申请号：US12976630

申请日：2010-12-22

申请人： Walid M. Hafez ,  Anisur Rahman ,  Chia-Hong Jan

发明人： Walid M. Hafez ,  Anisur Rahman ,  Chia-Hong Jan

IPC分类号： G11C7/00

CPC分类号： G11C7/00 ,  G11C17/16 ,  G11C17/18 ,  H03K19/173

摘要： Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments.

摘要翻译： 公开了用于实现利用高k /金属栅极n型或p型金属氧化物半导体（NMOS或PMOS）晶体管的偏置温度不稳定性（BTI）效应的非易失性存储器的技术和电路。 例如，存储器或可编程逻辑电路的编程位单元表现出由用于编程位单元的应用编程偏置产生的阈值电压偏移。 在一些情况下，施加第一编程偏置使得器件具有第一状态，并且施加第二编程偏置使得器件具有与第一状态不同的第二状态。 可以通过施加相反的极性应力来擦除编程的位单元，并通过多个周期重新编程。 根据一些实施例，位单元配置可以与列/行选择电路和/或读出电路结合使用。

公开(公告)号：US20130288444A1

公开(公告)日：2013-10-31

申请号：US13927694

申请日：2013-06-26

申请人： Walid M. Hafez ,  Chia-Hong Jan ,  Anisur Rahman

发明人： Walid M. Hafez ,  Chia-Hong Jan ,  Anisur Rahman

IPC分类号： H01L29/78

CPC分类号： H01L29/45 ,  H01L21/823418 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

摘要： An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.

摘要翻译： 一种装置包括具有金属栅极和漏极阱的第一器件，其经受在漏极阱和栅极之下的沟道之间的接点处的漏极接触电压从10V降低至4-6V的串联电阻。 该装置包括设置在排水井上方和排水井上的层间电介质层（ILD0）和排水井中的自对准硅排放接头。 该设备还包括位于与低于第一设备的电压工作的第一设备不同的区域中的后续设备。

公开(公告)号：US08487376B2

公开(公告)日：2013-07-16

申请号：US12858770

申请日：2010-08-18

申请人： Walid M. Hafez ,  Chia-Hong Jan ,  Anisur Rahman

发明人： Walid M. Hafez ,  Chia-Hong Jan ,  Anisur Rahman

IPC分类号： H01L29/76

CPC分类号： H01L29/45 ,  H01L21/823418 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

摘要： An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.

公开(公告)号：US08432751B2

公开(公告)日：2013-04-30

申请号：US12976630

申请日：2010-12-22

申请人： Walid M. Hafez ,  Anisur Rahman ,  Chia-Hong Jan

发明人： Walid M. Hafez ,  Anisur Rahman ,  Chia-Hong Jan

IPC分类号： G11C7/00

CPC分类号： G11C7/00 ,  G11C17/16 ,  G11C17/18 ,  H03K19/173

摘要： Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments.

摘要翻译： 公开了用于实现利用高k /金属栅极n型或p型金属氧化物半导体（NMOS或PMOS）晶体管的偏置温度不稳定性（BTI）效应的非易失性存储器的技术和电路。 例如，存储器或可编程逻辑电路的编程位单元表现出由用于编程位单元的应用编程偏置产生的阈值电压偏移。 在一些情况下，施加第一编程偏置使得器件具有第一状态，并且施加第二编程偏置使得器件具有与第一状态不同的第二状态。 可以通过施加相反的极性应力来擦除编程的位单元，并通过多个周期重新编程。 根据一些实施例，位单元配置可以与列/行选择电路和/或读出电路结合使用。

公开(公告)号：US20120043609A1

公开(公告)日：2012-02-23

申请号：US12858770

申请日：2010-08-18

申请人： Walid M. Hafez ,  Chia-Hong Jan ,  Anisur Rahman

发明人： Walid M. Hafez ,  Chia-Hong Jan ,  Anisur Rahman

IPC分类号： H01L27/088 ,  H01L21/768

CPC分类号： H01L29/45 ,  H01L21/823418 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

摘要： An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.

摘要翻译： 一种装置包括具有金属栅极和漏极阱的第一器件，其经受在漏极阱和栅极之下的沟道之间的接点处的漏极接触电压从10V降低至4-6V的串联电阻。 该装置包括设置在排水井上方和排水井上的层间电介质层（ILD0）和排水井中的自对准硅排放接头。 该设备还包括位于与低于第一设备的电压工作的第一设备不同的区域中的后续设备。

公开(公告)号：US20100164603A1

公开(公告)日：2010-07-01

申请号：US12319104

申请日：2008-12-30

申请人： Walid M. Hafez ,  Chia-Hong Jan ,  Jie-Feng Lin ,  Chetan Prasad ,  Sangwoo Pae ,  Zhanping Chen ,  Anisur Rahman

发明人： Walid M. Hafez ,  Chia-Hong Jan ,  Jie-Feng Lin ,  Chetan Prasad ,  Sangwoo Pae ,  Zhanping Chen ,  Anisur Rahman

IPC分类号： H01H37/76 ,  H01L29/00

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

摘要： A programmable anti-fuse element includes a substrate (224), an N-well (426) in the substrate, an electrically insulating layer (427) over the N-well, and a gate electrode (430) over the electrically insulating layer. The gate electrode has n-type doping so that the N-well is able to substantially contain within its boundaries a current generated following a programming event of the programmable anti-fuse element. In the same or another embodiment, a twice-programmable fuse element (100) includes a metal gate fuse (110) and an oxide anti-fuse (120) such as the programmable anti-fuse element just described.

摘要翻译： 可编程抗熔丝元件包括衬底（224），衬底中的N阱（426），在N阱上的电绝缘层（427）以及电绝缘层上的栅电极（430）。 栅电极具有n型掺杂，使得N阱能够在其边界内基本上包含在可编程反熔丝元件的编程事件之后产生的电流。 在相同或另一个实施例中，两次可编程熔丝元件（100）包括金属栅极熔丝（110）和氧化物反熔丝（120），例如刚刚描述的可编程反熔丝元件。

公开(公告)号：US08829592B2

公开(公告)日：2014-09-09

申请号：US12967436

申请日：2010-12-14

申请人： Walid M. Hafez ,  Anisur Rahman

发明人： Walid M. Hafez ,  Anisur Rahman

IPC分类号： H01L29/788 ,  H01L29/423 ,  G11C16/04 ,  H01L29/792 ,  H01L49/02 ,  H01L29/51 ,  H01L21/28

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L21/28282 ,  H01L28/40 ,  H01L29/4234 ,  H01L29/513 ,  H01L45/00

摘要： A non-volatile storage element and a method of forming the storage element. The non-volatile storage element comprises: a first electrode including a first material having a first work function; a second electrode including a second material having a second work function higher than the first work function; a first dielectric disposed between the first electrode and the second electrode, the first dielectric having a first bandgap; a second dielectric disposed between the first dielectric and the second electrode, the second dielectric having a second bandgap wider than the first bandgap and being disposed such that a quantum well is created in the first dielectric; and a third dielectric disposed between the first electrode and the first dielectric, the third dielectric being thinner than the second dielectric and having a third bandgap wider than the first bandgap.

摘要翻译： 非易失性存储元件和形成存储元件的方法。 非易失性存储元件包括：第一电极，其包括具有第一功函数的第一材料; 第二电极，包括具有高于第一功函数的第二功函数的第二材料; 设置在所述第一电极和所述第二电极之间的第一电介质，所述第一电介质具有第一带隙; 设置在所述第一电介质和所述第二电极之间的第二电介质，所述第二电介质具有比所述第一带隙宽的第二带隙，并且被布置为使得在所述第一电介质中产生量子阱; 以及设置在所述第一电极和所述第一电介质之间的第三电介质，所述第三电介质比所述第二电介质薄，并且具有比所述第一带隙宽的第三带隙。

公开(公告)号：US20120146124A1

公开(公告)日：2012-06-14

申请号：US12967436

申请日：2010-12-14

申请人： Walid M. Hafez ,  Anisur Rahman

发明人： Walid M. Hafez ,  Anisur Rahman

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L21/28282 ,  H01L28/40 ,  H01L29/4234 ,  H01L29/513 ,  H01L45/00

摘要： A non-volatile storage element and a method of forming the storage element. The non-volatile storage element comprises: a first electrode including a first material having a first work function; a second electrode including a second material having a second work function higher than the first work function; a first dielectric disposed between the first electrode and the second electrode, the first dielectric having a first bandgap; a second dielectric disposed between the first dielectric and the second electrode, the second dielectric having a second bandgap wider than the first bandgap and being disposed such that a quantum well is created in the first dielectric; and a third dielectric disposed between the first electrode and the first dielectric, the third dielectric being thinner than the second dielectric and having a third bandgap wider than the first bandgap.

摘要翻译： 非易失性存储元件和形成存储元件的方法。 非易失性存储元件包括：第一电极，其包括具有第一功函数的第一材料; 第二电极，包括具有高于第一功函数的第二功函数的第二材料; 设置在所述第一电极和所述第二电极之间的第一电介质，所述第一电介质具有第一带隙; 设置在所述第一电介质和所述第二电极之间的第二电介质，所述第二电介质具有比所述第一带隙宽的第二带隙，并且被布置为使得在所述第一电介质中产生量子阱; 以及设置在所述第一电极和所述第一电介质之间的第三电介质，所述第三电介质比所述第二电介质薄，并且具有比所述第一带隙宽的第三带隙。