公开(公告)号：US08610210B2

公开(公告)日：2013-12-17

申请号：US12840201

申请日：2010-07-20

申请人： Hiroshi Ohta ,  Yasuto Sumi ,  Kiyoshi Kimura ,  Wataru Sekine ,  Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Nana Hatano ,  Miho Watanabe

发明人： Hiroshi Ohta ,  Yasuto Sumi ,  Kiyoshi Kimura ,  Wataru Sekine ,  Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Nana Hatano ,  Miho Watanabe

IPC分类号： H01L29/66

CPC分类号： H01L29/66712 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/7811

摘要： According to one embodiment, a power semiconductor device includes a first semiconductor layer, and first, second and third semiconductor regions. The first semiconductor layer has a first conductivity type. The first semiconductor regions have a second conductivity type, and are formed with periodicity in a lateral direction in a second semiconductor layer of the first conductivity type. The second semiconductor layer is provided on a major surface of the first semiconductor layer in a device portion with a main current path formed in a vertical direction generally perpendicular to the major surface and in a terminal portion provided around the device portion. The second semiconductor region has the first conductivity type and is a portion of the second semiconductor layer sandwiched between adjacent ones of the first semiconductor regions. The third semiconductor regions have the second conductivity type and are provided below the first semiconductor regions in the terminal portion.

摘要翻译： 根据一个实施例，功率半导体器件包括第一半导体层以及第一，第二和第三半导体区域。 第一半导体层具有第一导电类型。 第一半导体区域具有第二导电类型，并且在第一导电类型的第二半导体层中在横向方向上形成周期性。 第二半导体层设置在器件部分的第一半导体层的主表面上，其主电流通道形成在大体上垂直于主表面的垂直方向上，以及设置在器件部分周围的端子部分中。 第二半导体区域具有第一导电类型，并且是夹在相邻的第一半导体区域中的第二半导体层的一部分。 第三半导体区域具有第二导电类型并且设置在端子部分中的第一半导体区域的下方。

公开(公告)号：US20100123186A1

公开(公告)日：2010-05-20

申请号：US12620045

申请日：2009-11-17

申请人： Hiroshi Ohta ,  Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Nana Hatano ,  Miho Watanabe

发明人： Hiroshi Ohta ,  Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Nana Hatano ,  Miho Watanabe

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/7395 ,  H01L29/7811 ,  Y10S257/901

摘要： In a vertical power semiconductor device having the super junction structure both in a device section and a terminal section, an n-type impurity layer is formed on the outer peripheral surface in the super junction structure. This allows an electric field on the outer peripheral surface of the super junction structure region to be reduced. Accordingly, a reliable vertical power semiconductor device of a high withstand voltage can be provided.

摘要翻译： 在器件部分和端子部分都具有超结结构的垂直功率半导体器件中，在超结结构的外周表面上形成n型杂质层。 这允许减小超结结构区域的外周表面上的电场。 因此，可以提供高耐受电压的可靠的垂直功率半导体器件。

公开(公告)号：US08232593B2

公开(公告)日：2012-07-31

申请号：US12714002

申请日：2010-02-26

申请人： Wataru Saito ,  Syotaro Ono ,  Hiroshi Ohta ,  Munehisa Yabuzaki ,  Nana Hatano ,  Miho Watanabe

发明人： Wataru Saito ,  Syotaro Ono ,  Hiroshi Ohta ,  Munehisa Yabuzaki ,  Nana Hatano ,  Miho Watanabe

IPC分类号： H01L29/78 ,  H01L29/06

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7395 ,  H01L29/861 ,  H01L29/8611

摘要： A power semiconductor device according to an embodiment of the present invention includes a first semiconductor layer of a first or second conductivity type, a second semiconductor layer of the first conductivity type formed on the first semiconductor layer, a third semiconductor layer of the second conductivity type selectively formed on a surface of the second semiconductor layer, at least one trench formed in a periphery of the third semiconductor layer on the surface of the second semiconductor layer, a depth of a bottom surface of the at least one trench being deeper than a bottom surface of the third semiconductor layer, and shallower than a top surface of the first semiconductor layer, and some or all of the at least one trench being in contact with a side surface of the third semiconductor layer, at least one insulator buried in the at least one trench, a first main electrode electrically connected to the first semiconductor layer, and a second main electrode electrically connected to the third semiconductor layer.

摘要翻译： 根据本发明实施例的功率半导体器件包括第一或第二导电类型的第一半导体层，形成在第一半导体层上的第一导电类型的第二半导体层，第二导电类型的第三半导体层 选择性地形成在第二半导体层的表面上，形成在第二半导体层的表面上的第三半导体层的周边中的至少一个沟槽，至少一个沟槽的底表面的深度比底部 表面，并且比第一半导体层的顶表面浅，并且至少一个沟槽的一些或全部与第三半导体层的侧表面接触，至少一个绝缘体埋在第三半导体层 至少一个沟槽，与第一半导体层电连接的第一主电极和电连接的第二主电极 引导到第三半导体层。

公开(公告)号：US08125023B2

公开(公告)日：2012-02-28

申请号：US12620045

申请日：2009-11-17

申请人： Hiroshi Ohta ,  Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Nana Hatano ,  Miho Watanabe

发明人： Hiroshi Ohta ,  Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Nana Hatano ,  Miho Watanabe

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/7395 ,  H01L29/7811 ,  Y10S257/901

摘要： In a vertical power semiconductor device having the super junction structure both in a device section and a terminal section, an n-type impurity layer is formed on the outer peripheral surface in the super junction structure. This allows an electric field on the outer peripheral surface of the super junction structure region to be reduced. Accordingly, a reliable vertical power semiconductor device of a high withstand voltage can be provided.

摘要翻译： 在器件部分和端子部分都具有超结结构的垂直功率半导体器件中，在超结结构的外周表面上形成n型杂质层。 这允许减小超结结构区域的外周表面上的电场。 因此，可以提供高耐受电压的可靠的垂直功率半导体器件。

公开(公告)号：US07919824B2

公开(公告)日：2011-04-05

申请号：US12403881

申请日：2009-03-13

申请人： Syotaro Ono ,  Wataru Saito ,  Nana Hatano ,  Masaru Izumisawa ,  Yasuto Sumi ,  Hiroshi Ohta ,  Wataru Sekine ,  Miho Watanabe

发明人： Syotaro Ono ,  Wataru Saito ,  Nana Hatano ,  Masaru Izumisawa ,  Yasuto Sumi ,  Hiroshi Ohta ,  Wataru Sekine ,  Miho Watanabe

IPC分类号： H01L27/088

CPC分类号： H01L29/66712 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/7395 ,  H01L29/7811

摘要： A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region have an impurity amount such that it becomes smaller as being closer to the circumference of the corner part.

摘要翻译： 半导体器件包括具有交替设置在半导体衬底上的第一导电型第一半导体柱区域和第二导电型第二半导体柱区域的超结区域。 终端区域中的第一半导体柱区域和第二半导体柱区域具有由半导体衬底的顶表面上的第一半导体柱区域和第二半导体柱区域的交替层叠形成的叠层形式。 终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域显示杂质浓度分布，使得多个杂质浓度峰值周期性出现。 终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域具有使得随着角部更靠近圆周而变小的杂质量。

公开(公告)号：US20100187604A1

公开(公告)日：2010-07-29

申请号：US12692527

申请日：2010-01-22

申请人： SYOTARO ONO ,  Wataru Saito ,  Nana Hatano ,  Hiroshi Ohta ,  Miho Watanabe

发明人： SYOTARO ONO ,  Wataru Saito ,  Nana Hatano ,  Hiroshi Ohta ,  Miho Watanabe

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7397

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type on the semiconductor substrate, and a plurality of second semiconductor regions of a second conductivity type disposed separately in the first semiconductor region. A difference between a charge quantity expressed by an integral value of a net activated doping concentration in the second semiconductor regions in the surface direction of the semiconductor substrate and a charge quantity expressed by an integral value of a net activated doping concentration in the first semiconductor region in the surface direction of the semiconductor substrate is always a positive quantity and becomes larger from the depth of the first junction plane to a depth of a second junction plane on an opposite side from the first junction plane.

摘要翻译： 半导体器件包括第一导电类型的半导体衬底，半导体衬底上的第一导电类型的第一半导体区域和分开设置在第一半导体区域中的多个第二导电类型的第二半导体区域。 由半导体衬底的表面方向上的第二半导体区域中的净活化掺杂浓度的积分值表示的电荷量与由第一半导体区域中的净活化掺杂浓度的积分值表示的电荷量之间的差异 在半导体基板的表面方向总是为正量，并且从第一接合面的深度到与第一接合面相反的一侧的第二接合面的深度变得更大。

公开(公告)号：US08159023B2

公开(公告)日：2012-04-17

申请号：US12692527

申请日：2010-01-22

申请人： Syotaro Ono ,  Wataru Saito ,  Nana Hatano ,  Hiroshi Ohta ,  Miho Watanabe

发明人： Syotaro Ono ,  Wataru Saito ,  Nana Hatano ,  Hiroshi Ohta ,  Miho Watanabe

IPC分类号： H01L29/00

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7397

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type on the semiconductor substrate, and a plurality of second semiconductor regions of a second conductivity type disposed separately in the first semiconductor region. A difference between a charge quantity expressed by an integral value of a net activated doping concentration in the second semiconductor regions in the surface direction of the semiconductor substrate and a charge quantity expressed by an integral value of a net activated doping concentration in the first semiconductor region in the surface direction of the semiconductor substrate is always a positive quantity and becomes larger from the depth of the first junction plane to a depth of a second junction plane on an opposite side from the first junction plane.

摘要翻译： 半导体器件包括第一导电类型的半导体衬底，半导体衬底上的第一导电类型的第一半导体区域和分开设置在第一半导体区域中的多个第二导电类型的第二半导体区域。 由半导体衬底的表面方向上的第二半导体区域中的净活化掺杂浓度的积分值表示的电荷量与由第一半导体区域中的净活化掺杂浓度的积分值表示的电荷量之间的差异 在半导体基板的表面方向总是为正量，并且从第一接合面的深度到与第一接合面相反的一侧的第二接合面的深度变得更大。

公开(公告)号：US08030706B2

公开(公告)日：2011-10-04

申请号：US12540192

申请日：2009-08-12

申请人： Miho Watanabe ,  Masaru Izumisawa ,  Yasuto Sumi ,  Hiroshi Ohta ,  Wataru Sekine ,  Wataru Saito ,  Syotaro Ono ,  Nana Hatano

发明人： Miho Watanabe ,  Masaru Izumisawa ,  Yasuto Sumi ,  Hiroshi Ohta ,  Wataru Sekine ,  Wataru Saito ,  Syotaro Ono ,  Nana Hatano

IPC分类号： H01L29/66

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/7802

摘要： A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value ΔN (=NA−NB) obtained by subtracting an impurity amount NB per unit length of each of the third semiconductor layers from an impurity amount NA per unit length of each of the second semiconductor layers, a difference value ΔNC1 which is the difference value ΔN in the first region of the device part, a difference value ΔNC2 which is the difference value ΔN in the second region of the device part, and a difference value ΔNT which is the difference value ΔN in the terminal part satisfy a relationship of ΔNC1>ΔNT>ΔNC2.

摘要翻译： 根据本发明实施例的半导体器件包括器件部分和端子部分。 该器件包括第一半导体层，以及形成在第一半导体层上的第二和第三半导体层，并且沿着与第一半导体层的表面平行的方向交替布置，其中器件部分设置有第一区域和第二半导体层 区域，其中每一个包括第二半导体层和至少一个第三半导体层中的至少一个，并且关于通过从每单位长度减去杂质量NB获得的差值Dgr; N（= NA-NB） 从每个第二半导体层的每单位长度的杂质量NA中的每个第三半导体层的差分值＆Dgr; NC1，其是器件部分的第一区域中的差值＆Dgr; N，差值＆Dgr ;作为装置部分的第二区域中的差值Dgr; N的NC2，作为终端部分中的差值Dgr; N的差值＆Dgr; NT满足关系 的＆Dgr; NC1>＆Dgr; NT>＆Dgr; NC2。

公开(公告)号：US07755138B2

公开(公告)日：2010-07-13

申请号：US12537219

申请日：2009-08-06

申请人： Wataru Saito ,  Syotaro Ono ,  Nana Hatano ,  Hiroshi Ohta ,  Miho Watanabe

发明人： Wataru Saito ,  Syotaro Ono ,  Nana Hatano ,  Hiroshi Ohta ,  Miho Watanabe

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7806

摘要： A semiconductor device of the invention includes: a super junction structure of an n-type pillar layer and a p-type pillar layer; a base layer provided on the p-type pillar layer; a source layer selectively provided on a surface of the base layer; a gate insulating film provided on a portion being in contact with the base layer, a portion being in contact with the source layer and a portion being in contact with the n-type pillar layer on a portion of a junction between the n-type pillar layer and the p-type pillar layer; a control electrode provided opposed to the base layer, the source layer and the n-type pillar layer through the gate insulating film; and a source electrode electrically connected to the base layer, the source layer and the n-type layer. The source electrode is contact with the surface of the n-type pillar layer located between the control electrodes to form a Schottky junction.

摘要翻译： 本发明的半导体器件包括：n型柱层和p型柱层的超结结构; 设置在p型支柱层上的基底层; 源层选择性地设置在基层的表面上; 设置在与所述基底层接触的部分上的栅极绝缘膜，与所述源极层接触的部分和在所述n型支柱的接合部的一部分上与所述n型支柱层接触的部分 层和p型支柱层; 控制电极，其通过所述栅极绝缘膜与所述基极层，所述源极层和所述n型支柱层相对设置; 以及与基极层，源极层和n型层电连接的源电极。 源电极与位于控制电极之间的n型支柱层的表面接触以形成肖特基结。

公开(公告)号：US07989910B2

公开(公告)日：2011-08-02

申请号：US12252872

申请日：2008-10-16

申请人： Wataru Saito ,  Syotaro Ono ,  Masaru Izumisawa ,  Yasuto Sumi ,  Hiroshi Ohta ,  Wataru Sekine ,  Nana Hatano

发明人： Wataru Saito ,  Syotaro Ono ,  Masaru Izumisawa ,  Yasuto Sumi ,  Hiroshi Ohta ,  Wataru Sekine ,  Nana Hatano

IPC分类号： H01L29/66

CPC分类号： H01L29/0634 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/7811

摘要： A semiconductor device includes an n+ type semiconductor substrate 1 and a super junction region that has, on the top of the substrate 1, an n and p type pillar regions 2 and 3 provided alternately. The device also includes, in the top surface of the super junction region, a p type base region 4 and an n type source layer 5. The device also includes a gate electrode 7 on the region 4 and layer 5 via a gate-insulating film 6, a drain electrode 9 on the bottom of the substrate 1, and a source electrode 8 on the top of the substrate 1. In the top surface of the super junction region in the terminal region, a RESURF region 10 is formed. The RESURF region has a comb-like planar shape with repeatedly-formed teeth having tips facing the end portion of the terminal region.

摘要翻译： 半导体器件包括n +型半导体衬底1和超结区，其在衬底1的顶部上交替设置n和p型柱状区域2,3。 该器件还在超结区域的顶表面中包括ap型基极区域4和n型源极层5.该器件还包括位于区域4上的栅电极7和通过栅极绝缘膜6的层5 ，基板1底部的漏电极9以及基板1顶部的源极8.在端子区域的超结区域的上表面形成有RESURF区域10。 RESURF区域具有梳状平面形状，具有重复形成的齿，其尖端面向终端区域的端部。