公开(公告)号：US08610210B2

公开(公告)日：2013-12-17

申请号：US12840201

申请日：2010-07-20

申请人： Hiroshi Ohta ,  Yasuto Sumi ,  Kiyoshi Kimura ,  Wataru Sekine ,  Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Nana Hatano ,  Miho Watanabe

发明人： Hiroshi Ohta ,  Yasuto Sumi ,  Kiyoshi Kimura ,  Wataru Sekine ,  Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Nana Hatano ,  Miho Watanabe

IPC分类号： H01L29/66

CPC分类号： H01L29/66712 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/7811

摘要： According to one embodiment, a power semiconductor device includes a first semiconductor layer, and first, second and third semiconductor regions. The first semiconductor layer has a first conductivity type. The first semiconductor regions have a second conductivity type, and are formed with periodicity in a lateral direction in a second semiconductor layer of the first conductivity type. The second semiconductor layer is provided on a major surface of the first semiconductor layer in a device portion with a main current path formed in a vertical direction generally perpendicular to the major surface and in a terminal portion provided around the device portion. The second semiconductor region has the first conductivity type and is a portion of the second semiconductor layer sandwiched between adjacent ones of the first semiconductor regions. The third semiconductor regions have the second conductivity type and are provided below the first semiconductor regions in the terminal portion.

摘要翻译： 根据一个实施例，功率半导体器件包括第一半导体层以及第一，第二和第三半导体区域。 第一半导体层具有第一导电类型。 第一半导体区域具有第二导电类型，并且在第一导电类型的第二半导体层中在横向方向上形成周期性。 第二半导体层设置在器件部分的第一半导体层的主表面上，其主电流通道形成在大体上垂直于主表面的垂直方向上，以及设置在器件部分周围的端子部分中。 第二半导体区域具有第一导电类型，并且是夹在相邻的第一半导体区域中的第二半导体层的一部分。 第三半导体区域具有第二导电类型并且设置在端子部分中的第一半导体区域的下方。

公开(公告)号：US20120074491A1

公开(公告)日：2012-03-29

申请号：US13234802

申请日：2011-09-16

申请人： Hiroshi OHTA ,  Yasuto SUMI ,  Kiyoshi KIMURA ,  Junji SUZUKI ,  Hiroyuki IRIFUNE ,  Wataru SAITO ,  Syotaro ONO

发明人： Hiroshi OHTA ,  Yasuto SUMI ,  Kiyoshi KIMURA ,  Junji SUZUKI ,  Hiroyuki IRIFUNE ,  Wataru SAITO ,  Syotaro ONO

IPC分类号： H01L27/088

CPC分类号： H01L29/78 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/42372 ,  H01L29/7811 ,  H01L29/7813

摘要： In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other.

摘要翻译： 通常，根据一个实施例，功率半导体器件包括在第一半导体层上的第一导电类型的第一柱状区域，第二柱状区域和外延层。 第一支柱区域由第一导电类型的多个第一支柱层和沿第一方向交替布置的第一导电类型的多个第二支柱层组成。 第二柱状区域沿着第一方向与第一柱状区域相邻，并且具有第二导电型的第三柱状层，第一导电型的第四柱状层和第二导电型的第五柱状层 沿着第一个方向。 多个第二导电类型的第二基极层分别电连接到第三柱层和第五柱层上并彼此间隔开。

公开(公告)号：US20110291181A1

公开(公告)日：2011-12-01

申请号：US13149345

申请日：2011-05-31

申请人： Hiroyuki IRIFUNE ,  Yasuto Sumi ,  Kiyoshi Kimura ,  Hiroshi Ohta

发明人： Hiroyuki IRIFUNE ,  Yasuto Sumi ,  Kiyoshi Kimura ,  Hiroshi Ohta

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66712 ,  H01L29/0626 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

摘要： According to one embodiment, a semiconductor device including a cell region and a terminal region includes a first semiconductor region of a first conductivity type, semiconductor pillars of the first and a second conductivity type, a second semiconductor region of the second conductivity type, and a third semiconductor region of the first conductivity type. The semiconductor pillars of the first and second conductivity type are and arranged alternately on the first semiconductor region. The second semiconductor region is provided on the semiconductor pillar of the second conductivity type. The third semiconductor region is provided on the second semiconductor region. A semiconductor pillar other than a semiconductor pillar most proximal to the terminal region is provided in a stripe configuration. The semiconductor pillar most proximal to the terminal region includes regions having a high and a low impurity concentration. The regions are provided alternately.

摘要翻译： 根据一个实施例，包括单元区域和端子区域的半导体器件包括第一导电类型的第一半导体区域，第一和第二导电类型的半导体柱，第二导电类型的第二半导体区域和 第一导电类型的第三半导体区域。 第一和第二导电类型的半导体柱交替地布置在第一半导体区域上。 第二半导体区域设置在第二导电类型的半导体柱上。 第三半导体区域设置在第二半导体区域上。 最靠近端子区域的半导体柱以外的半导体柱设置成条状。 最靠近末端区域的半导体柱包括具有高和低杂质浓度的区域。 这些区域交替地设置。

公开(公告)号：US20100230750A1

公开(公告)日：2010-09-16

申请号：US12789008

申请日：2010-05-27

申请人： Wataru SAITO ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta

发明人： Wataru SAITO ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.

摘要翻译： 功率半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层和形成在第一半导体层上的第二导电类型的第三半导体层，并且沿着平行于第一半导体层的表面的至少一个方向交替布置; 第一主电极; 选择性地形成在第二半导体层的表面和第三半导体层的表面上的第二导电类型的第四半导体层; 选择性地形成在第四半导体层的表面中的第一导电类型的第五半导体层; 第二主电极; 和控制电极。 第二和第三半导体层中的至少一个具有沿着一个方向的掺杂剂浓度分布，掺杂剂浓度分布在其两端以外的位置处具有局部最小值。

公开(公告)号：US20080135929A1

公开(公告)日：2008-06-12

申请号：US11933869

申请日：2007-11-01

申请人： Wataru SAITO ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta

发明人： Wataru SAITO ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813

摘要： A power semiconductor device includes: a semiconductor substrate; a gate insulating film; a control electrode insulated from the semiconductor substrate by the gate insulating film; a first main electrode provided on a lower surface side of the semiconductor substrate; and a second main electrode provided on an upper surface side of the semiconductor substrate. The semiconductor substrate includes: a first first-conductivity-type semiconductor layer with its lower surface connected to the first main electrode; a second first-conductivity-type semiconductor layer and a third second-conductivity-type semiconductor layer formed on the first first-conductivity-type semiconductor layer and alternately arranged parallel to the upper surface of the semiconductor substrate; a trench formed in a directly overlying region of the third second-conductivity-type semiconductor layer, with part of the second main electrode buried in the trench; a fourth second-conductivity-type semiconductor layer selectively formed in a surface of the second first-conductivity-type semiconductor layer and connected to the second main electrode; a fifth first-conductivity-type semiconductor layer selectively formed in a surface of the fourth second-conductivity-type semiconductor layer and connected to the second main electrode; and a sixth second-conductivity-type semiconductor layer formed at a bottom of the trench and connected to the second main electrode. Impurity concentration in the sixth second-conductivity-type semiconductor layer is higher than impurity concentration in the fourth second-conductivity-type semiconductor layer, and lower surface of the sixth second-conductivity-type semiconductor layer is located below lower surface of the fourth second-conductivity-type semiconductor layer.

摘要翻译： 功率半导体器件包括：半导体衬底; 栅极绝缘膜; 通过栅极绝缘膜与半导体衬底绝缘的控制电极; 设置在所述半导体基板的下表面侧的第一主电极; 以及设置在半导体衬底的上表面侧的第二主电极。 半导体衬底包括：第一第一导电型半导体层，其下表面连接到第一主电极; 形成在第一第一导电型半导体层上的第二第一导电型半导体层和第三第二导电型半导体层，并且交替地平行于半导体基板的上表面布置; 形成在所述第三第二导电型半导体层的直接覆盖区域中的沟槽，其中所述第二主电极的一部分埋在所述沟槽中; 选择性地形成在所述第二第一导电型半导体层的表面并连接到所述第二主电极的第四第二导电型半导体层; 第五第一导电型半导体层，选择性地形成在所述第四第二导电型半导体层的表面上，并连接到所述第二主电极; 以及形成在所述沟槽的底部并连接到所述第二主电极的第六第二导电型半导体层。 第六第二导电型半导体层中的杂质浓度高于第四第二导电型半导体层中的杂质浓度，第六第二导电型半导体层的下表面位于第四第二导电型半导体层的下表面下方 导电型半导体层。

公开(公告)号：US20070272979A1

公开(公告)日：2007-11-29

申请号：US11748869

申请日：2007-05-15

申请人： Wataru SAITO ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta ,  Wataru Sekine

发明人： Wataru SAITO ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta ,  Wataru Sekine

IPC分类号： H01L29/76

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41741 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7722 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/8611

摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.

摘要翻译： 半导体器件包括：第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域，与半导体层的主表面上的第一半导体柱区域相邻设置，第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及 第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。 高电阻半导体层的掺杂浓度低于第一半导体柱区域。 边界区域设置在设备中心区域和边缘终端部分之间。 边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。

公开(公告)号：US08643056B2

公开(公告)日：2014-02-04

申请号：US13229203

申请日：2011-09-09

申请人： Kiyoshi Kimura ,  Yasuto Sumi ,  Hiroshi Ohta ,  Hiroyuki Irifune

发明人： Kiyoshi Kimura ,  Yasuto Sumi ,  Hiroshi Ohta ,  Hiroyuki Irifune

IPC分类号： H01L29/66

CPC分类号： H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/872

摘要： A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers. The plurality of third second-conductivity-type pillar layers are arranged on the first epitaxial layer.

摘要翻译： 功率半导体器件包括第一导电类型的第一半导体层，第一漂移层和第二漂移层。 第一漂移层包括第一导电类型的第一外延层，多个第一第一导电型柱层和多个第一第二导电型柱层。 第二漂移层形成在第一漂移层上，并且包括第一导电类型的第二外延层，多个第二第二导电型柱层，多个第二第一导电型柱层，多个第二导电型柱层 第三第二导电型柱层和多个第三第一导电型柱层。 多个第二第二导电型柱层与第一第二导电型柱层连接。 多个第二第一导电型柱层与第一第一导电型柱层连接。 多个第三第二导电型柱层布置在第一外延层上。

公开(公告)号：US20110233656A1

公开(公告)日：2011-09-29

申请号：US13049634

申请日：2011-03-16

申请人： Hiroshi OHTA ,  Yasuto Sumi ,  Klyoshi Kimura

发明人： Hiroshi OHTA ,  Yasuto Sumi ,  Klyoshi Kimura

IPC分类号： H01L29/78 ,  H01L21/425

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/66712

摘要： According to one embodiment, a semiconductor device includes a semiconductor layer of a first conductivity type, first semiconductor pillar regions of the first conductivity type and second semiconductor pillar regions of a second conductivity type, a semiconductor region of the first conductivity type, a base region of the second conductivity type, a source region, a first main electrode, a second main electrode and a control electrode. The second semiconductor pillar region includes a plurality of semiconductor regions of the second conductivity type. A difference is provided between peak values of impurity concentration profiles of an uppermost and a lowermost semiconductor regions of the plurality of semiconductor regions, and in the alternately arranging direction of the first and second semiconductor pillar regions, maximum width of the uppermost semiconductor region is generally equal to or narrower than maximum width of the lowermost semiconductor region.

摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的半导体层，第一导电类型的第一半导体柱区域和第二导电类型的第二半导体柱区域，第一导电类型的半导体区域，基极区域 的第二导电类型，源极区，第一主电极，第二主电极和控制电极。 第二半导体柱区域包括第二导电类型的多个半导体区域。 在多个半导体区域的最上半导体区域和最下半导体区域的杂质浓度分布的峰值之间，在第一和第二半导体柱区域的交替排列方向上，最上半导体区域的最大宽度一般是 等于或窄于最低半导体区域的最大宽度。

公开(公告)号：US07989910B2

公开(公告)日：2011-08-02

申请号：US12252872

申请日：2008-10-16

申请人： Wataru Saito ,  Syotaro Ono ,  Masaru Izumisawa ,  Yasuto Sumi ,  Hiroshi Ohta ,  Wataru Sekine ,  Nana Hatano

发明人： Wataru Saito ,  Syotaro Ono ,  Masaru Izumisawa ,  Yasuto Sumi ,  Hiroshi Ohta ,  Wataru Sekine ,  Nana Hatano

IPC分类号： H01L29/66

CPC分类号： H01L29/0634 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/7811

摘要： A semiconductor device includes an n+ type semiconductor substrate 1 and a super junction region that has, on the top of the substrate 1, an n and p type pillar regions 2 and 3 provided alternately. The device also includes, in the top surface of the super junction region, a p type base region 4 and an n type source layer 5. The device also includes a gate electrode 7 on the region 4 and layer 5 via a gate-insulating film 6, a drain electrode 9 on the bottom of the substrate 1, and a source electrode 8 on the top of the substrate 1. In the top surface of the super junction region in the terminal region, a RESURF region 10 is formed. The RESURF region has a comb-like planar shape with repeatedly-formed teeth having tips facing the end portion of the terminal region.

摘要翻译： 半导体器件包括n +型半导体衬底1和超结区，其在衬底1的顶部上交替设置n和p型柱状区域2,3。 该器件还在超结区域的顶表面中包括ap型基极区域4和n型源极层5.该器件还包括位于区域4上的栅电极7和通过栅极绝缘膜6的层5 ，基板1底部的漏电极9以及基板1顶部的源极8.在端子区域的超结区域的上表面形成有RESURF区域10。 RESURF区域具有梳状平面形状，具有重复形成的齿，其尖端面向终端区域的端部。

公开(公告)号：US07919824B2

公开(公告)日：2011-04-05

申请号：US12403881

申请日：2009-03-13

申请人： Syotaro Ono ,  Wataru Saito ,  Nana Hatano ,  Masaru Izumisawa ,  Yasuto Sumi ,  Hiroshi Ohta ,  Wataru Sekine ,  Miho Watanabe

发明人： Syotaro Ono ,  Wataru Saito ,  Nana Hatano ,  Masaru Izumisawa ,  Yasuto Sumi ,  Hiroshi Ohta ,  Wataru Sekine ,  Miho Watanabe

IPC分类号： H01L27/088

CPC分类号： H01L29/66712 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/7395 ,  H01L29/7811

摘要： A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region have an impurity amount such that it becomes smaller as being closer to the circumference of the corner part.

摘要翻译： 半导体器件包括具有交替设置在半导体衬底上的第一导电型第一半导体柱区域和第二导电型第二半导体柱区域的超结区域。 终端区域中的第一半导体柱区域和第二半导体柱区域具有由半导体衬底的顶表面上的第一半导体柱区域和第二半导体柱区域的交替层叠形成的叠层形式。 终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域显示杂质浓度分布，使得多个杂质浓度峰值周期性出现。 终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域具有使得随着角部更靠近圆周而变小的杂质量。