DOWNHOLE FLUID RESISTIVITY SENSOR SYSTEMS AND METHODS
    1.
    发明申请
    DOWNHOLE FLUID RESISTIVITY SENSOR SYSTEMS AND METHODS 有权
    井下流体电阻传感器系统和方法

    公开(公告)号:US20150168582A1

    公开(公告)日:2015-06-18

    申请号:US14388193

    申请日:2012-03-28

    IPC分类号: G01V3/02 E21B49/08

    CPC分类号: G01V3/02 E21B49/08 G01V3/20

    摘要: Disclosed is a downhole fluid resistivity sensor that includes a ceramic cylinder having a fluid-contacting surface, and at least four metal pins that penetrate a wall of the ceramic cylinder at axially-spaced locations. The pins are bonded to the ceramic to form a pressure seal. The sensor may include a circuit that injects current into a fluid via an outer two of the pins, and measures a resulting voltage via an inner two of the pins. The circuit may also provide an indication of fluid resistivity based at least in part on the resulting voltage. At each of the axially-spaced locations, a set of multiple pins may penetrate the wall to contact the fluid at circumferentially-spaced positions. The fluid-contacting surface may be an inner surface or an outer surface of the ceramic cylinder. A downhole fluid resistivity measurement method is also described.

    摘要翻译: 公开了一种井下流体电阻率传感器,其包括具有流体接触表面的陶瓷圆筒,以及至少四个在轴向间隔开的位置处穿过陶瓷圆柱壁的金属销。 销钉结合到陶瓷上以形成压力密封。 传感器可以包括经由外部两个引脚将电流注入流体的电路,并且经由内部两个引脚测量所得到的电压。 该电路还可以至少部分地基于所得到的电压来提供流体电阻率的指示。 在每个轴向间隔的位置处,一组多个销可以穿透壁以在周向间隔的位置处接触流体。 流体接触表面可以是陶瓷圆筒的内表面或外表面。 还描述了井下流体电阻率测量方法。

    Downhole fluid resistivity sensor systems and methods
    2.
    发明授权
    Downhole fluid resistivity sensor systems and methods 有权
    井下流体电阻率传感器系统及方法

    公开(公告)号:US09575199B2

    公开(公告)日:2017-02-21

    申请号:US14388193

    申请日:2012-03-28

    IPC分类号: G01V3/02 G01V3/20 E21B49/08

    CPC分类号: G01V3/02 E21B49/08 G01V3/20

    摘要: Disclosed is a downhole fluid resistivity sensor that includes a ceramic cylinder having a fluid-contacting surface, and at least four metal pins that penetrate a wall of the ceramic cylinder at axially-spaced locations. The pins are bonded to the ceramic to form a pressure seal. The sensor may include a circuit that injects current into a fluid via an outer two of the pins, and measures a resulting voltage via an inner two of the pins. The circuit may also provide an indication of fluid resistivity based at least in part on the resulting voltage. At each of the axially-spaced locations, a set of multiple pins may penetrate the wall to contact the fluid at circumferentially-spaced positions. The fluid-contacting surface may be an inner surface or an outer surface of the ceramic cylinder. A downhole fluid resistivity measurement method is also described.

    摘要翻译: 公开了一种井下流体电阻率传感器,其包括具有流体接触表面的陶瓷圆筒,以及至少四个在轴向间隔开的位置处穿过陶瓷圆柱壁的金属销。 销钉结合到陶瓷上以形成压力密封。 传感器可以包括经由外部两个引脚将电流注入流体的电路,并且经由内部两个引脚测量所得到的电压。 该电路还可以至少部分地基于所得到的电压来提供流体电阻率的指示。 在每个轴向间隔的位置处,一组多个销可以穿透壁以在周向间隔的位置处接触流体。 流体接触表面可以是陶瓷圆筒的内表面或外表面。 还描述了井下流体电阻率测量方法。

    Method and system for crosstalk analysis
    7.
    发明授权
    Method and system for crosstalk analysis 失效
    串扰分析方法和系统

    公开(公告)号:US07761826B1

    公开(公告)日:2010-07-20

    申请号:US11782619

    申请日:2007-07-24

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5036

    摘要: Method and system for crosstalk analysis relating to a statistical crosstalk path delay model that fits into existing static timing framework with little overhead in performance and capacity. More realistic models or assumptions are utilized rather than the more aggressive and less likely deterministic model.

    摘要翻译: 与统计串扰路径延迟模型相关的串扰分析方法和系统,适用于现有的静态时序框架,性能和容量的开销很小。 使用更逼真的模型或假设,而不是更积极和不太可能的确定性模型。

    Statistical static timing analysis of signal with crosstalk induced delay change in integrated circuit
    8.
    发明授权
    Statistical static timing analysis of signal with crosstalk induced delay change in integrated circuit 有权
    统计静态时序分析信号与串扰引起的集成电路延迟变化

    公开(公告)号:US08244491B1

    公开(公告)日:2012-08-14

    申请号:US12343262

    申请日:2008-12-23

    申请人: Lizheng Zhang

    发明人: Lizheng Zhang

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5031 G06F2217/10

    摘要: A method is provided to evaluate crosstalk effect of aggressor switching upon victim net signal transition time within an integrated circuit comprising: combining a first probability density function (PDF) of first aggressor switching time in response to a first input signal to an aggressor net driver and a second aggressor switching time in response to a second input signal to the aggressor net driver; determining a delay change curve that represents a relationship between delay change of arrival time of a victim net signal transition and relative alignment of the aggressor net driver switching time and a victim net driver switching time; and determining a third PDF of delay change of a transition of the victim net signal based upon the combination and the delay change curve.

    摘要翻译: 提供了一种方法来评估攻击者切换对集成电路内的受害者网络信号转换时间的串扰效应,包括:将第一侵入者切换时间的第一概率密度函数(PDF)与响应于侵入者网络驱动器的第一输入信号相结合,以及 响应于对侵略者网络驱动器的第二输入信号的第二侵权者切换时间; 确定延迟变化曲线,其表示受害者网络信号转换的到达时间的延迟变化与侵略者网络驱动器切换时间的相对对准与受害者网络驱动器切换时间之间的关系; 以及基于所述组合和所述延迟变化曲线来确定所述受害者网络信号的转变的延迟变化的第三PDF。

    Efficient statistical timing analysis of circuits
    9.
    发明授权
    Efficient statistical timing analysis of circuits 有权
    电路的有效统计时序分析

    公开(公告)号:US07689954B2

    公开(公告)日:2010-03-30

    申请号:US11420322

    申请日:2006-05-25

    IPC分类号: G06F17/50

    摘要: Statistical timing analysis methods for circuits are described which compensate for circuit elements having correlated timing delays with a high degree of computational efficiency. An quadratic timing model is used to represent each delay element along a circuit path, wherein each element's delay has a first-order relationship to local variations and a second-order relationship to global variations. Propagation of the modeled delays through the circuit is efficiently done via straightforward ADD operations where an input propagates through another element in a circuit path, and via a MAX operation (or an approximation thereof) where two or more inputs merge at an intersection. The inputs to the MAX operator can be tested for gaussianity, and can be processed by the MAX operation (or its approximation) if they are substantially gaussian. Otherwise, they may be stored in a tuple for processing at later points along the circuit path.

    摘要翻译: 描述了用于补偿具有高计算效率的具有相关定时延迟的电路元件的电路的统计时序分析方法。 二次定时模型用于沿着电路路径表示每个延迟元件,其中每个元件的延迟与局部变化和与全局变化的二阶关系具有一级关系。 经由电路的建模延迟的传播通过简单的ADD操作有效地进行,其中输入传播通过电路路径中的另一元件,并且经由其中两个或多个输入在交叉点合并的MAX操作(或其近似)。 可以对MAX运算符的输入进行高斯测试,如果MAX操作基本为高斯,则可以通过MAX操作(或其近似)进行处理。 否则,它们可以存储在元组中,以便在沿着电路路径的稍后点进行处理。