公开(公告)号：US20230036531A1

公开(公告)日：2023-02-02

申请号：US17389272

申请日：2021-07-29

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Shishir KUMAR ,  Sagheer AHMAD ,  Abbas MORSHED ,  Aman GUPTA

IPC: G06F3/06

Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.

公开(公告)号：US20240291635A1

公开(公告)日：2024-08-29

申请号：US18113588

申请日：2023-02-23

Applicant: XILINX, INC.

Inventor： Abbas MORSHED ,  Ygal ARBEL ,  Balakrishna JAYADEV ,  Eun Mi KIM

IPC: H04L9/08 ,  G06F21/60

CPC classification number: H04L9/0825 ,  G06F21/602 ,  H04L9/0894

Abstract: Examples herein describe techniques for method of accessing encrypted data. The techniques include receiving, via a memory controller, a first memory request to a first memory region, where the first memory region is encrypted based on a first key, and incrementing, based on the first memory request, a first counter associated with the first key. The techniques further include, in response to determining that the first counter exceeds a first threshold, initiating a key rolling operation to cause the first memory region to be encrypted based on a second key. The techniques further include tracking an address range of the first memory region that has been encrypted based on the second key, and, in response to determining that an address of a second memory request is outside of the address range, causing the second memory request to be completed based on the first key.

公开(公告)号：US20240111704A1

公开(公告)日：2024-04-04

申请号：US17959903

申请日：2022-10-04

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Abbas MORSHED ,  Sagheer AHMAD

IPC: G06F13/40

CPC classification number: G06F13/4059 ,  G06F13/4022

Abstract: Embodiments herein describe a NoC where its internal switches have buffers with pods that can be assigned to different virtual channels. A subset of the pods in a buffer can be grouped together to form a VC. In this manner, different pod groups in a buffer can be assigned to different VCs (or to different types of NoC data units), where VCs that transmit wider data units can be assigned more pods than VCs that transmit narrower data units.

公开(公告)号：US20240281325A1

公开(公告)日：2024-08-22

申请号：US18111805

申请日：2023-02-20

Applicant: XILINX, INC.

Inventor： Ygal ARBEL ,  Jonathan JASPER ,  Abbas MORSHED

IPC: G06F11/10 ,  G06F12/0871 ,  G06F12/0891

CPC classification number: G06F11/1068 ,  G06F12/0871 ,  G06F12/0891

Abstract: An integrated circuit (IC) device includes processor circuitry configured to output a first memory command having a first memory address, and in-line error correction control (ILECC) circuitry configured to receive the first memory command and output the first memory command to a memory device. The ILECC circuitry includes an error correction code (ECC) cache configured to store a first local ECC associated with the first memory command in a first cache line.

公开(公告)号：US20220337923A1

公开(公告)日：2022-10-20

申请号：US17232207

申请日：2021-04-16

Applicant: XILINX, INC.

Inventor： Aman GUPTA ,  Sagheer AHMAD ,  Ygal ARBEL ,  Abbas MORSHED ,  Eun Mi KIM

IPC: H04Q3/00 ,  G06F13/40 ,  G06F13/16

Abstract: Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.

公开(公告)号：US20240333473A1

公开(公告)日：2024-10-03

申请号：US18126877

申请日：2023-03-27

Applicant: XILINX, INC.

Inventor： Abbas MORSHED ,  Ygal ARBEL

IPC: H04L9/06 ,  G06F12/1009 ,  G06F12/12

CPC classification number: H04L9/0637 ,  G06F12/1009 ,  G06F12/12 ,  H04L9/0631

Abstract: Some examples described herein provide for an encrypted data quantization apparatus and method, for example a memory controller to quantize encrypted data using a cache. One or more embodiments includes obtaining a first set of plaintext data bits to be stored in a memory device using an encryption scheme. A memory address for encrypted data bits to be stored in the memory device is identified for a first subset of plaintext data bits. A second set of plaintext data bits associated with the memory address is obtained from a cache, if present. The second set of plaintext data bits are modified according to the first set of plaintext data bits to be stored in the memory device to generate a third set of plaintext data bits that are then encoded according to the encryption scheme for storage in the memory device.

公开(公告)号：US20240045822A1

公开(公告)日：2024-02-08

申请号：US17879675

申请日：2022-08-02

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Ygal ARBEL ,  Sagheer AHMAD ,  Abbas MORSHED

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F2213/40

Abstract: Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transport memory mapped traffic amongst heterogeneous IC devices in a packetized, scalable, and configurable manner. An IC chip may include functional circuitry that exchanges memory-mapped traffic with an off-chip device, a NoC that packetizes and de-packetizes memory-mapped traffic and routes the packetized memory-mapped traffic between the functional circuitry and the off-chip device, and NoC inter-chip bridge (NICB) circuitry that interfaces between the NoC and the off-chip device over C2C interconnections. The NICB circuitry may be configurable in a full mode to map packetized memory-mapped traffic to the C2C interconnections in a 1:1 fashion and in a compressed to map packetized memory-mapped traffic to the C2C interconnections in a less-than 1:1 fashion.

公开(公告)号：US20210303508A1

公开(公告)日：2021-09-30

申请号：US16830142

申请日：2020-03-25

Applicant: XILINX, INC.

Inventor： Abbas MORSHED ,  Ygal ARBEL ,  Eun Mi KIM

IPC: G06F15/78 ,  G06F5/10 ,  G06F9/38 ,  G06F13/40

Abstract: Embodiments herein describe a SoC that includes a NoC that supports both strict and relax ordering requests. That is, some applications may require strict ordering where requests transmitted from the same ingress logic to different egress logic blocks are performed sequentially. However, other applications may not require strict ordering, such as interleaved writes to memory. In those applications, relax ordering can be used were the same ingress logic block can transmit multiple requests to different egress logic blocks in parallel. For example, an ingress logic block may receive a first request that is indicated as being a relaxed ordered request. After transmitting the request to an egress logic block, the ingress logic block may receive a second request. The ingress logic block can transmit the second request to a different egress logic block without waiting for a response for the first request.