公开(公告)号：US20240143891A1

公开(公告)日：2024-05-02

申请号：US17979649

申请日：2022-11-02

Applicant: XILINX, INC.

Inventor： Surya Rajendra Swamy Saranam CHONGALA ,  Nikhil Arun DHUME ,  Krishnan SRINIVASAN ,  Dinesh D. GAITONDE

IPC: G06F30/3953

CPC classification number: G06F30/3953

Abstract: Embodiments herein describe a network on chip (NoC) that implements multi-path routing (MPR) between an ingress logic block and an egress logic block. The multiple paths between the ingress and egress logic blocks can be assigned different alias destination IDs corresponding to the same destination ID. The NoC can use the alias destination IDs to route the packets along the different paths through interconnected switches in the NoC.

公开(公告)号：US20240345977A1

公开(公告)日：2024-10-17

申请号：US18134994

申请日：2023-04-14

Applicant: XILINX, INC.

Inventor： Dinesh D. GAITONDE ,  Aashish TRIPATHI ,  Ashit DEBNATH ,  Davis Boyd MOORE ,  Maithilee Rajendra KULKARNI ,  Abhishek Kumar JAIN

IPC: G06F13/40

CPC classification number: G06F13/4059 ,  G06F13/4068

Abstract: A 3D device includes a first semiconductor chip and a second semiconductor chip stacked vertically. The first semiconductor chip includes a first plurality of tiles. The second semiconductor chip includes a second plurality of tiles. A bus electrically couples each of the first plurality of tiles to a corresponding one of the second plurality of tiles based on assignments of the first plurality of tiles and the second plurality of tiles to tile-to-tile pairs that define a minimized sum of bus delays among each possible tile-to-tile pairs. In each tile-to-tile pair, a net electrically couples each of a first plurality of pins to a corresponding one of a second plurality of pins based on assignments of the first plurality of pins to the second plurality of pins that define a minimized sum of net delays among each possible pin-to-pin pairs.

公开(公告)号：US20240329126A1

公开(公告)日：2024-10-03

申请号：US18128947

申请日：2023-03-30

Applicant: XILINX, INC.

Inventor： Dinesh D. GAITONDE ,  Matthew H. KLEIN ,  Himanshu VERMA ,  Chirag RAVISHANKAR ,  Maithilee Rajendra KULKARNI

IPC: G01R31/28

CPC classification number: G01R31/2896 ,  G01R31/287

Abstract: Embodiments herein describe assigning integrated circuits with defects as variants of the integrated circuit design. Each variant can deactivate different circuitry in the integrated circuit design. A location of the defect can be matched to a variant that has a deactivated region that covers the defect. The integrated circuit can then be assigned to that variant.

公开(公告)号：US20230409204A1

公开(公告)日：2023-12-21

申请号：US18230117

申请日：2023-08-03

Applicant: XILINX, INC.

Inventor： Abhishek Kumar JAIN ,  Henri FRAISSE ,  Dinesh D. GAITONDE

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: A method includes receiving a value and an identifier from a first memory and hashing the identifier to produce a memory block identifier. The method also includes routing, based on the memory block identifier, a read request to a memory block of a plurality of memory blocks and updating the value received from the first memory based on a property received from the memory block in response to the read request. The memory further includes storing the updated value in the first memory.