公开(公告)号：US09325489B2

公开(公告)日：2016-04-26

申请号：US14135071

申请日：2013-12-19

Applicant: Xilinx, Inc.

Inventor： Cheng-Hsiang Hsieh ,  Kun-Yung Chang ,  Jafar Savoj

IPC: H04L7/00 ,  H04L7/033 ,  H04L25/03

CPC classification number: H04L7/0025 ,  H04L7/0062 ,  H04L7/0331 ,  H04L7/0334 ,  H04L25/03057 ,  H04L25/03885

Abstract: A data receiver implemented in an integrated circuit is described. The data receiver comprises an input receiving a data signal; a first equalization circuit coupled to receive the data signal, wherein the first equalization circuit is used to receive the data of the data signal; and a second equalization circuit coupled to receive the data signal, wherein the second equalization circuit is used to adjust a clock phase offset.

Abstract translation: 描述了在集成电路中实现的数据接收器。 数据接收机包括接收数据信号的输入端; 耦合以接收所述数据信号的第一均衡电路，其中所述第一均衡电路用于接收所述数据信号的数据; 以及耦合以接收所述数据信号的第二均衡电路，其中所述第二均衡电路用于调整时钟相位偏移。

公开(公告)号：US08836391B2

公开(公告)日：2014-09-16

申请号：US13633584

申请日：2012-10-02

Applicant: Xilinx, Inc.

Inventor： Parag Upadhyaya ,  Jafar Savoj ,  Anthony Torza

IPC: H03L7/06 ,  H03L7/087 ,  H03L7/089

CPC classification number: H03L7/087 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/1976 ,  H04J3/0685 ,  H04L27/0014 ,  H04L2027/0059 ,  H04L2027/0067

Abstract: A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-N phase lock loop; and utilizing, by the at least one fractional-N phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-N phase lock loop are contained on a single integrated circuit.

Abstract translation: 一种用于并行有线收发机的同步时钟产生方法，包括：向至少一个解码器输入至少一个数字频率失配数; 使用所述至少一个解码器解码所述至少一个数字频率失配数，以获得表示与至少一个信号相关联的发射频率的至少一个数字分频器数; 将至少一个数字分频器编号输入到至少一个小数N相锁定环中; 以及利用所述至少一个分数N锁相环使用所述至少一个数字分频器编号和由参考振荡器产生的模拟参考信号，以产生在所述发射频率处的结果信号; 其中所述至少一个解码器和所述至少一个分数N相锁相环包含在单个集成电路上。

公开(公告)号：US20140091843A1

公开(公告)日：2014-04-03

申请号：US13633584

申请日：2012-10-02

Applicant: XILINX, INC.

Inventor： Parag Upadhyaya ,  Jafar Savoj ,  Anthony Torza

IPC: H03L7/093

CPC classification number: H03L7/087 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/1976 ,  H04J3/0685 ,  H04L27/0014 ,  H04L2027/0059 ,  H04L2027/0067

Abstract: A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-N phase lock loop; and utilizing, by the at least one fractional-N phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-N phase lock loop are contained on a single integrated circuit.

Abstract translation: 一种用于并行有线收发机的同步时钟产生方法，包括：向至少一个解码器输入至少一个数字频率失配数; 使用所述至少一个解码器解码所述至少一个数字频率失配数，以获得表示与至少一个信号相关联的发射频率的至少一个数字分频器数; 将至少一个数字分频器编号输入到至少一个小数N相锁定环中; 以及利用所述至少一个分数N锁相环使用所述至少一个数字分频器编号和由参考振荡器产生的模拟参考信号，以产生在所述发射频率处的结果信号; 其中所述至少一个解码器和所述至少一个分数N相锁相环包含在单个集成电路上。

公开(公告)号：US08736325B1

公开(公告)日：2014-05-27

申请号：US13629377

申请日：2012-09-27

Applicant: Xilinx, Inc.

Inventor： Jafar Savoj ,  Kun-Yung Chang

IPC: H03L7/06

CPC classification number: H03L7/1974

Abstract: A system for wide frequency range clock generation, includes: a phase lock loop (PLL) to generate a signal having a frequency; at least one fractional-N divider to divide the frequency of the signal; and a multiplexer to receive the signal from the PLL and an output signal from the at least one fractional-N divider, and to select the signal from the PLL or the output signal from the at least one fractional-N divider as a selected signal.

Abstract translation: 一种用于宽频率时钟产生的系统，包括：产生具有频率的信号的锁相环（PLL）; 至少一个小数N分频器来分频信号的频率; 以及多路复用器，用于从PLL接收信号和来自至少一个分数N分频器的输出信号，并且选择来自PLL的信号或来自至少一个小数N分频器的输出信号作为选择的信号。

公开(公告)号：US20150180642A1

公开(公告)日：2015-06-25

申请号：US14135071

申请日：2013-12-19

Applicant: Xilinx, Inc.

Inventor： Cheng-Hsiang Hsieh ,  Kun-Yung Chang ,  Jafar Savoj

IPC: H04L7/00 ,  H04L7/033 ,  H04L25/03

CPC classification number: H04L7/0025 ,  H04L7/0062 ,  H04L7/0331 ,  H04L7/0334 ,  H04L25/03057 ,  H04L25/03885

Abstract: A data receiver implemented in an integrated circuit is described. The data receiver comprises an input receiving a data signal; a first equalization circuit coupled to receive the data signal, wherein the first equalization circuit is used to receive the data of the data signal; and a second equalization circuit coupled to receive the data signal, wherein the second equalization circuit is used to adjust a clock phase offset.

Abstract translation: 描述了在集成电路中实现的数据接收器。 数据接收机包括接收数据信号的输入端; 耦合以接收所述数据信号的第一均衡电路，其中所述第一均衡电路用于接收所述数据信号的数据; 以及耦合以接收所述数据信号的第二均衡电路，其中所述第二均衡电路用于调整时钟相位偏移。

公开(公告)号：US08841948B1

公开(公告)日：2014-09-23

申请号：US13830729

申请日：2013-03-14

Applicant: Xilinx, Inc.

Inventor： Jun-Chau Chien ,  Wayne Fang ,  Parag Upadhyaya ,  Jafar Savoj ,  Kun-Yung Chang

IPC: H03L7/06 ,  H03L7/07

CPC classification number: H03L7/081 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/24

Abstract: An apparatus relates generally to an injection-controlled-locked phase-locked loop (“ICL-PLL”) is disclosed. In this apparatus, a delay-locked loop is coupled to an injection-locked phase-locked loop. An injection-locked oscillator of the injection-locked phase-locked loop is in a feedback loop path of the delay-locked loop.

Abstract translation: 一种装置一般涉及一种注射锁定锁相环（“ICL-PLL”）。 在该装置中，延迟锁定环耦合到注入锁定的锁相环。 注入锁相环的注入锁定振荡器处于延迟锁定环路的反馈回路中。