公开(公告)号：US11605886B1

公开(公告)日：2023-03-14

申请号：US17133518

申请日：2020-12-23

Applicant: XILINX, INC.

Inventor： Gamal Refai-Ahmed ,  Chi-Yi Chao ,  Lik Tsang ,  Jens Weis ,  Brendan Farley ,  Anthony Torza ,  Suresh Ramalingam

IPC: H01Q1/42 ,  H01L23/427 ,  H01Q1/02

Abstract: An antenna assembly is provided having passive cooling elements that enable compact design. In one example, an antenna assembly is provided that includes a heat sink assembly having an interior side and an exterior side, an antenna array, an antenna circuit board, and a radome. The antenna circuit board includes at least one integrated circuit (IC) die. The IC die has a conductive primary heat dissipation path to the interior side of the heat sink assembly. The radome is coupled to the heat sink assembly and encloses the antenna circuit board and the antenna array between the radome and the heat sink assembly. The heat sink assembly includes a metal base plate and at least a first heat pipe embedded with the metal base plate. The first heat pipe is disposed between the metal base plate and the IC die.

公开(公告)号：US10147664B2

公开(公告)日：2018-12-04

申请号：US15495720

申请日：2017-04-24

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Daniel Elftmann ,  Brian D. Philofsky ,  Anthony Torza

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/367 ,  H05K1/18 ,  H01L23/433 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00

Abstract: Chip packages and electronic devices are provided that include a heat sink flexibly interfaced with a die for enhanced temperature control. In one example, a solid state electronic assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate and a heat sink mounted over the first IC die. The heat sink includes a thermally conductive plate and a first thermal carrier. The first thermal carrier has a first end mechanically fixed to the conductive plate. The first thermal carrier has a second end cantilevered from the conductive plate. The second end is in conductive contact with a top surface of the first IC die.

公开(公告)号：US20180308783A1

公开(公告)日：2018-10-25

申请号：US15495720

申请日：2017-04-24

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Daniel Elftmann ,  Brian D. Philofsky ,  Anthony Torza

IPC: H01L23/367 ,  H05K1/18 ,  H01L23/433 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L23/3672 ,  H01L23/3736 ,  H01L23/433 ,  H01L23/4338 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/72 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29293 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32221 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H05K1/181 ,  H05K2201/10378 ,  H05K2201/10734 ,  H01L2924/0665 ,  H01L2924/01006

Abstract: Chip packages and electronic devices are provided that include a heat sink flexibly interfaced with a die for enhanced temperature control. In one example, a solid state electronic assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate and a heat sink mounted over the first IC die. The heat sink includes a thermally conductive plate and a first thermal carrier. The first thermal carrier has a first end mechanically fixed to the conductive plate. The first thermal carrier has a second end cantilevered from the conductive plate. The second end is in conductive contact with a top surface of the first IC die.

公开(公告)号：US09378174B2

公开(公告)日：2016-06-28

申请号：US14070851

申请日：2013-11-04

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Anthony Torza

IPC: G06F13/42 ,  H03M9/00 ,  H04J3/06 ,  H04L25/14

CPC classification number: G06F13/4282 ,  H03M9/00 ,  H04J3/0685 ,  H04L25/14

Abstract: An apparatus relates generally to serializer-deserializers. In such an apparatus, a first serializer-deserializer has a first data path and a data eye path. The first data path is coupled to a first data out interface of the first serializer-deserializer. A second serializer-deserializer has a second data path. The second data path is coupled to a second data out interface of the second serializer-deserializer. The data eye path of the first serializer-deserializer is coupled to the second data path of the second serializer-deserializer.

Abstract translation: 一种装置一般涉及串行器 - 解串器。 在这种装置中，第一串行器 - 解串器具有第一数据路径和数据眼路径。 第一数据路径耦合到第一串行器 - 解串器的第一数据输出接口。 第二个串行器 - 解串器具有第二数据路径。 第二数据路径耦合到第二串行器 - 解串器的第二数据输出接口。 第一串行器 - 解串器的数据眼路径耦合到第二串行器 - 解串器的第二数据路径。

公开(公告)号：US20150127877A1

公开(公告)日：2015-05-07

申请号：US14070851

申请日：2013-11-04

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Anthony Torza

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  H03M9/00 ,  H04J3/0685 ,  H04L25/14

Abstract: An apparatus relates generally to serializer-deserializers. In such an apparatus, a first serializer-deserializer has a first data path and a data eye path. The first data path is coupled to a first data out interface of the first serializer-deserializer. A second serializer-deserializer has a second data path. The second data path is coupled to a second data out interface of the second serializer-deserializer. The data eye path of the first serializer-deserializer is coupled to the second data path of the second serializer-deserializer.

Abstract translation: 一种装置一般涉及串行器 - 解串器。 在这种装置中，第一串行器 - 解串器具有第一数据路径和数据眼路径。 第一数据路径耦合到第一串行器 - 解串器的第一数据输出接口。 第二个串行器 - 解串器具有第二数据路径。 第二数据路径耦合到第二串行器 - 解串器的第二数据输出接口。 第一串行器 - 解串器的数据眼路径耦合到第二串行器 - 解串器的第二数据路径。

公开(公告)号：US11373929B1

公开(公告)日：2022-06-28

申请号：US16780305

申请日：2020-02-03

Applicant: XILINX, INC.

Inventor： Gamal Refai-Ahmed ,  Chi-Yi Chao ,  Suresh Ramalingam ,  Hoa Lap Do ,  Anthony Torza ,  Brian Philofsky ,  Arun Kumar Varadarajan Rajagopal

IPC: H01L23/473 ,  H01L23/467 ,  H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L23/427

Abstract: A cooling plate assembly and electronic device having the same are provided which utilize active and passive cooling devices for improved thermal management of one or more chip package assemblies included in the electronic device. In one example, a cooling plate assembly is provided that includes a cooling plate having a first surface and an opposing second surface, a first active cooling device coupled to the first surface of the cooling plate, and a first passive cooling device coupled to the second surface of the cooling plate.

公开(公告)号：US11328976B1

公开(公告)日：2022-05-10

申请号：US16808023

申请日：2020-03-03

Applicant: XILINX, INC.

Inventor： Gamal Refai-Ahmed ,  Chi-Yi Chao ,  Suresh Ramalingam ,  Hoa Lap Do ,  Anthony Torza ,  Brian D. Philofsky

IPC: H01L23/367 ,  H01L23/467 ,  H01L23/473 ,  H01L23/42

Abstract: Some examples described herein provide for three-dimensional (3D) thermal management apparatuses for thermal energy dissipation of thermal energy generated by an electronic device. In an example, an apparatus includes a thermal management apparatus that includes a primary base, a passive two-phase flow thermal carrier, and fins. The thermal carrier has a carrier base and one or more sidewalls extending from the carrier base. The carrier base and the one or more sidewalls are a single integral piece. The primary base is attached to the thermal carrier. The carrier base has an exterior surface that at least a portion of which defines a die contact region. The thermal carrier has an internal volume aligned with the die contact region. A fluid is disposed in the internal volume. The fins are attached to and extend from the one or more sidewalls of the thermal carrier.

公开(公告)号：US10262920B1

公开(公告)日：2019-04-16

申请号：US15369607

申请日：2016-12-05

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Brian D. Philofsky ,  Anthony Torza

IPC: H01L23/22 ,  H01L23/24 ,  H01L23/427 ,  H01L23/055 ,  H01L23/367 ,  H01L23/10

Abstract: Chip packages and electronic devices are provided that include a thermal capacitance element that improves the operation of IC dies at elevated temperatures. In one example, a chip package is provided that includes an integrated circuit (IC) die, a lid thermally connected to the IC die, and a thermal capacitance element thermally connected to the lid. The thermal capacitance element includes a container and a capacitance material sealingly disposed in the container. The capacitance material has a phase transition temperature that is between 80 and 100 percent of a maximum designed operating temperature in degrees Celsius of the IC die.

公开(公告)号：US08836391B2

公开(公告)日：2014-09-16

申请号：US13633584

申请日：2012-10-02

Applicant: Xilinx, Inc.

Inventor： Parag Upadhyaya ,  Jafar Savoj ,  Anthony Torza

IPC: H03L7/06 ,  H03L7/087 ,  H03L7/089

CPC classification number: H03L7/087 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/1976 ,  H04J3/0685 ,  H04L27/0014 ,  H04L2027/0059 ,  H04L2027/0067

Abstract: A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-N phase lock loop; and utilizing, by the at least one fractional-N phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-N phase lock loop are contained on a single integrated circuit.

Abstract translation: 一种用于并行有线收发机的同步时钟产生方法，包括：向至少一个解码器输入至少一个数字频率失配数; 使用所述至少一个解码器解码所述至少一个数字频率失配数，以获得表示与至少一个信号相关联的发射频率的至少一个数字分频器数; 将至少一个数字分频器编号输入到至少一个小数N相锁定环中; 以及利用所述至少一个分数N锁相环使用所述至少一个数字分频器编号和由参考振荡器产生的模拟参考信号，以产生在所述发射频率处的结果信号; 其中所述至少一个解码器和所述至少一个分数N相锁相环包含在单个集成电路上。

公开(公告)号：US20140091843A1

公开(公告)日：2014-04-03

申请号：US13633584

申请日：2012-10-02

Applicant: XILINX, INC.

Inventor： Parag Upadhyaya ,  Jafar Savoj ,  Anthony Torza

IPC: H03L7/093

CPC classification number: H03L7/087 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/1976 ,  H04J3/0685 ,  H04L27/0014 ,  H04L2027/0059 ,  H04L2027/0067

Abstract: A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-N phase lock loop; and utilizing, by the at least one fractional-N phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-N phase lock loop are contained on a single integrated circuit.

Abstract translation: 一种用于并行有线收发机的同步时钟产生方法，包括：向至少一个解码器输入至少一个数字频率失配数; 使用所述至少一个解码器解码所述至少一个数字频率失配数，以获得表示与至少一个信号相关联的发射频率的至少一个数字分频器数; 将至少一个数字分频器编号输入到至少一个小数N相锁定环中; 以及利用所述至少一个分数N锁相环使用所述至少一个数字分频器编号和由参考振荡器产生的模拟参考信号，以产生在所述发射频率处的结果信号; 其中所述至少一个解码器和所述至少一个分数N相锁相环包含在单个集成电路上。