公开(公告)号：US08552547B2

公开(公告)日：2013-10-08

申请号：US13741320

申请日：2013-01-14

Applicant: Xintec Inc.

Inventor： Wen-Cheng Chien ,  Ching-Yu Ni ,  Shu-Ming Chang

IPC: H01L23/48

CPC classification number: B05D1/36 ,  B81B2207/096 ,  B81C1/00301 ,  H01L21/56 ,  H01L21/6835 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L27/14618 ,  H01L31/02002 ,  H01L31/0203 ,  H01L33/486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/00

Abstract: An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.

Abstract translation: 本发明的实施例提供了一种形成电子器件封装的方法，该方法包括提供具有上表面和相对下表面的载体衬底; 从所述载体基板的上表面形成空腔; 将具有导电电极的电子设备设置在空腔中; 在所述空腔中形成填充层，其中所述填充层围绕所述电子设备; 将载体基板从下表面变薄到预定厚度; 在电子设备或载体衬底中形成至少一个通孔; 以及在所述通孔的侧壁上形成导电层，其中所述导电层与所述导电电极电连接。

公开(公告)号：US09190362B2

公开(公告)日：2015-11-17

申请号：US14325812

申请日：2014-07-08

Applicant: XINTEC INC.

Inventor： Wen-Cheng Chien ,  Wen-Ken Huang ,  Chien-Hung Liu ,  Joey Lai

IPC: H01L21/00 ,  H01L23/00 ,  H01L27/146

CPC classification number: H01L23/562 ,  H01L24/05 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/02235 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

Abstract: The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad.

Abstract translation: 本发明提供一种芯片封装及其制造方法。 在一个实施例中，芯片封装包括：衬底，其上具有半导体器件和导电焊盘; 填充形成在所述衬底中的沟槽的绝缘体环，其中所述绝缘体环围绕所述导电焊盘下方的中间层; 以及设置在所述基板的背面下方并与导电焊盘电连接的导电层。

公开(公告)号：US08643198B2

公开(公告)日：2014-02-04

申请号：US13741318

申请日：2013-01-14

Applicant: Xintec Inc.

Inventor： Wen-Cheng Chien ,  Ching-Yu Ni ,  Shu-Ming Chang

IPC: B05D1/36

CPC classification number: B05D1/36 ,  B81B2207/096 ,  B81C1/00301 ,  H01L21/56 ,  H01L21/6835 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L27/14618 ,  H01L31/02002 ,  H01L31/0203 ,  H01L33/486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/00

Abstract: An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode.

Abstract translation: 本发明的实施例提供了一种形成电子器件封装的方法，该方法包括提供具有上表面和相对下表面的载体衬底; 从所述载体基板的上表面形成空腔; 将具有导电电极的电子设备设置在空腔中; 在所述空腔中形成填充层，其中所述填充层围绕所述电子设备; 将载体基板从下表面变薄到预定厚度; 在电子设备或载体衬底中形成至少一个通孔; 以及在所述通孔的侧壁上形成导电层，其中所述导电层与所述导电电极电连接。