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    Power MOSFET package
    1.
    发明授权
    Power MOSFET package 有权
    功率MOSFET封装

    公开(公告)号：US08766431B2

    公开(公告)日：2014-07-01

    申请号：US13828537

    申请日：2013-03-14

    Applicant: Xintec Inc.

    Inventor： Baw-Ching Perng ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Ji Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

    IPC: H01L23/04

    CPC classification number: H01L29/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/492 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2224/05099

    Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.

    Abstract translation: 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

    Chip package and fabrication method thereof
    3.
    发明授权
    Chip package and fabrication method thereof 有权
    芯片封装及其制造方法

    公开(公告)号：US08822325B2

    公开(公告)日：2014-09-02

    申请号：US13958398

    申请日：2013-08-02

    Applicant: Xintec Inc.

    Inventor： Ching-Yu Ni ,  Chia-Ming Cheng ,  Nan-Chun Lin

    IPC: H01L23/485 ,  H01L21/60

    CPC classification number: H01L23/498 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/06 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

    Abstract translation: 根据本发明的实施例提供了芯片封装及其制造方法。 芯片封装包括含有芯片并具有器件面积和外围焊盘区域的半导体衬底。 多个导电焊盘设置在外围接合焊盘区域处，并且钝化层形成在半导体衬底上以露出导电焊盘。 在器件区域的钝化层上形成绝缘保护层。 封装层设置在绝缘保护层上方以在外围接合焊盘区域露出导电焊盘和钝化层。 该方法包括在切割过程中形成绝缘保护层以覆盖多个导电焊盘，并且通过封装层的开口去除导电焊盘上的绝缘保护层。

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