公开(公告)号：US20140199830A1

公开(公告)日：2014-07-17

申请号：US14214408

申请日：2014-03-14

Applicant: XINTEC INC.

Inventor： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Long-Sheng YEOU

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein a sidewall of the hole is substantially perpendicular to the lower surface of the substrate, and the sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

Abstract translation: 根据本发明的实施例，提供了芯片封装。 芯片封装包括：具有上表面和下表面的基板; 位于所述基板的下表面下方的多个导电垫; 位于导电垫之间的电介质层; 从衬底的上表面延伸到下表面的沟槽; 从所述沟槽的底部延伸到所述衬底的下表面的孔，其中所述孔的侧壁基本上垂直于所述衬底的下表面，并且所述孔的侧壁或所述底部露出所述导电垫的一部分 ; 以及导电层，其位于所述孔中并电连接到至少一个所述导电焊盘。

公开(公告)号：US20150318348A1

公开(公告)日：2015-11-05

申请号：US14699261

申请日：2015-04-29

Applicant: XINTEC INC.

Inventor： Yu-Lin YEN ,  Sheng-Hao CHIANG ,  Hung-Chang CHEN ,  Ho-Ku LAN ,  Chen-Mei FAN

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0642 ,  H01L21/76229 ,  H01L27/1463 ,  H01L27/14683

Abstract: A semiconductor structure includes a substrate, a dam element, a first isolation layer, a second isolation layer, and a conductive layer. The substrate has a conductive pad, a trench, a sidewall, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the second surface. The trench has a first opening at the first surface, and has a second opening at the second surface. The dam element is located on the second surface and covers the second opening. The dam element has a concave portion that is at the second opening. The first isolation layer is located on a portion of the sidewall. The second isolation layer is located on the first surface and the sidewall that is not covered by the first isolation layer, such that an interface is formed between the first and second isolation layers.

Abstract translation: 半导体结构包括基板，阻挡元件，第一隔离层，第二隔离层和导电层。 衬底具有导电焊盘，沟槽，侧壁，第一表面和与第一表面相对的第二表面。 导电垫位于第二表面上。 沟槽在第一表面具有第一开口，并且在第二表面具有第二开口。 坝体元件位于第二表面并覆盖第二开口。 坝体元件具有在第二开口处的凹入部分。 第一隔离层位于侧壁的一部分上。 第二隔离层位于不被第一隔离层覆盖的第一表面和侧壁上，使得在第一和第二隔离层之间形成界面。

公开(公告)号：US20140199835A1

公开(公告)日：2014-07-17

申请号：US14214389

申请日：2014-03-14

Applicant: XINTEC INC.

Inventor： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Long-Sheng YEOU

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/13025 ,  H01L2224/9202 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein an upper sidewall of the hole inclines to the lower surface of the substrate, and a lower sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

Abstract translation: 根据本发明的实施例，提供了芯片封装。 芯片封装包括：具有上表面和下表面的基板; 位于所述基板的下表面下方的多个导电垫; 位于导电垫之间的电介质层; 从衬底的上表面延伸到下表面的沟槽; 从所述沟槽的底部延伸到所述衬底的下表面的孔，其中所述孔的上侧壁倾斜到所述衬底的下表面，并且所述孔的下侧壁或底部暴露所述导电垫的一部分 ; 以及导电层，其位于所述孔中并电连接到至少一个所述导电焊盘。