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    Scalable scan architecture for multi-circuit block arrays
    1.
    发明授权
    Scalable scan architecture for multi-circuit block arrays 有权

    公开(公告)号：US11639962B1

    公开(公告)日：2023-05-02

    申请号：US17199874

    申请日：2021-03-12

    Applicant: Xilinx, Inc.

    Inventor： Niravkumar Patel ,  Amitava Majumdar ,  Partho Tapan Chaudhuri

    IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3187 ,  G06F11/27

    Abstract: An integrated circuit (IC) can include a plurality of circuit blocks, wherein each circuit block includes design for testability (DFT) circuitry. The DFT circuitry can include a scan interface, wherein each scan interface is uniform with the scan interface of each other circuit block of the plurality of circuit blocks, an embedded deterministic test circuit coupled to the scan interface, wherein the embedded deterministic test circuit couples to circuitry under test, and a scan response analyzer coupled to the scan interface. The scan response analyzer is configured to operate in a selected scan response capture mode selected from a plurality of scan response capture modes. The IC can include a global scan router connected to the scan interfaces of the plurality of circuit blocks. The global scan router is configured to activate a subset of the plurality of circuit blocks in parallel for a scan test.

    Circuit architecture for expanded design for testability functionality
    2.
    发明授权
    Circuit architecture for expanded design for testability functionality 有权

    公开(公告)号：US11263377B1

    公开(公告)日：2022-03-01

    申请号：US17219174

    申请日：2021-03-31

    Applicant: Xilinx, Inc.

    Inventor： Amitava Majumdar ,  Albert Shih-Huai Lin ,  Partho Tapan Chaudhuri ,  Niravkumar Patel

    IPC: G06F30/333 ,  G06F30/3308 ,  G06F30/398 ,  G06F11/00 ,  G01R31/28 ,  H01L25/00 ,  H03K19/00 ,  G06F115/08 ,  G06F11/08

    Abstract: A circuit architecture for expanded design for testability functionality is provided that includes an Intellectual Property (IP) core for use with a design for an integrated circuit (IC). The IP core provides an infrastructure harness circuit configured to control expanded design for testability functions available within the IC. An instance of the IP core can be included in a circuit block of the design for the IC. The infrastructure harness circuit can include an outward facing interface configured to connect to circuitry outside of the circuit block and an inward facing interface configured to connect to circuitry within the circuit block. The instance of the IP core can be parameterized to configure the infrastructure harness circuit to control a plurality of functions selected from the expanded design for testability functions based on a user parameterization of the instance of the IP core.

    Integrated circuit chip testing interface with reduced signal wires
    5.
    发明授权
    Integrated circuit chip testing interface with reduced signal wires 有权

    公开(公告)号：US11860228B2

    公开(公告)日：2024-01-02

    申请号：US17742363

    申请日：2022-05-11

    Applicant: XILINX, INC.

    Inventor： Albert Shih-Huai Lin ,  Niravkumar Patel ,  Amitava Majumdar ,  Jane Wang Sowards

    IPC: G01R31/3185 ,  G01R31/317

    CPC classification number: G01R31/318555 ,  G01R31/31727 ,  G01R31/318572

    Abstract: An integrated circuit (IC) chip device includes testing interface circuity and testing circuitry to test the operation of the IC chips of the IC chip device. The IC chip device includes a first IC chip that comprises first testing circuitry. The first testing circuitry receives a mode select signal, a clock signal, and encoded signals, and comprises finite state machine (FSM) circuitry, decoder circuitry, and control circuitry. The FSM circuitry determines an instruction based on the mode select signal and the clock signal. The decoder circuitry decodes the encoded signals to generate a decoded signal. The control circuitry generates a control signal from the instruction and the decoded signal. The control signal indicates a test to be performed by the first testing circuitry.

    Programmable dynamic clock stretch for at-speed debugging of integrated circuits
    6.
    发明授权
    Programmable dynamic clock stretch for at-speed debugging of integrated circuits 有权

    公开(公告)号：US11290095B1

    公开(公告)日：2022-03-29

    申请号：US17330042

    申请日：2021-05-25

    Applicant: Xilinx, Inc.

    Inventor： Niravkumar Patel ,  Amitava Majumdar

    IPC: G06F1/00 ,  H03K5/156 ,  H03K19/173 ,  H03K5/05 ,  H03K5/24 ,  G06F1/08

    Abstract: An integrated circuit can include one or more clock controllers. Each clock controller corresponds to a different clock signal of a set of one or more clock signals of the integrated circuit. Each clock controller is configured to implement a clock stretch mode that generates a modified clock signal having a frequency that is less than the clock signal. The integrated circuit can include a trigger circuit configured to enable selected ones of the one or more clock controllers to implement the clock stretch mode. The trigger circuit and the one or more clock controllers are hardwired and are programmable using control infrastructure circuitry of the integrated circuit.

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