公开(公告)号：US08971468B1

公开(公告)日：2015-03-03

申请号：US14064539

申请日：2013-10-28

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini

IPC: H04L7/00 ,  H04L1/00

CPC classification number: H04L1/205 ,  H04L1/0071

Abstract: The methods and apparatus disclosed herein provide an operative system for increasing the resolution of serial DRUs based on interleaved free running oversamplers. In particular, this system uses incoming data to measure and to compensate the skew between two or more free running oversamplers (e.g., SerDes), without the need for any hardware design requirement relating to the precision of the relative skew of the oversamplers.

Abstract translation: 本文公开的方法和装置提供了一种用于基于交错自由运行的过采样器来增加串行DRU的分辨率的操作系统。 特别地，该系统使用输入数据来测量和补偿两个或更多个自由运行的过采样器（例如，SerDes）之间的偏斜，而不需要与过采样器的相对偏斜的精度相关的任何硬件设计要求。

公开(公告)号：US10832757B1

公开(公告)日：2020-11-10

申请号：US16279851

申请日：2019-02-19

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Giovanni Guasti

IPC: G11C8/00 ,  G11C11/4076 ,  G11C7/22 ,  G06F1/10

Abstract: A receiver implemented in an integrated circuit device is described. The receiver circuit comprises a first receiver circuit configured to receive first data, wherein the first receiver circuit comprises a first memory element configured to receive the first data in response to a first clock signal; a latency mirror circuit configured to receive second data, wherein the latency mirror circuit comprises a second memory element configured to receive the second data in response to a second clock signal; and a latency control circuit configured to detect a latency in the second data, wherein the latency control circuit adjusts a phase of the first clock signal used to receive the first data in the first receiver circuit.

公开(公告)号：US09378174B2

公开(公告)日：2016-06-28

申请号：US14070851

申请日：2013-11-04

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Anthony Torza

IPC: G06F13/42 ,  H03M9/00 ,  H04J3/06 ,  H04L25/14

CPC classification number: G06F13/4282 ,  H03M9/00 ,  H04J3/0685 ,  H04L25/14

Abstract: An apparatus relates generally to serializer-deserializers. In such an apparatus, a first serializer-deserializer has a first data path and a data eye path. The first data path is coupled to a first data out interface of the first serializer-deserializer. A second serializer-deserializer has a second data path. The second data path is coupled to a second data out interface of the second serializer-deserializer. The data eye path of the first serializer-deserializer is coupled to the second data path of the second serializer-deserializer.

Abstract translation: 一种装置一般涉及串行器 - 解串器。 在这种装置中，第一串行器 - 解串器具有第一数据路径和数据眼路径。 第一数据路径耦合到第一串行器 - 解串器的第一数据输出接口。 第二个串行器 - 解串器具有第二数据路径。 第二数据路径耦合到第二串行器 - 解串器的第二数据输出接口。 第一串行器 - 解串器的数据眼路径耦合到第二串行器 - 解串器的第二数据路径。

公开(公告)号：US20150127877A1

公开(公告)日：2015-05-07

申请号：US14070851

申请日：2013-11-04

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Anthony Torza

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  H03M9/00 ,  H04J3/0685 ,  H04L25/14

Abstract: An apparatus relates generally to serializer-deserializers. In such an apparatus, a first serializer-deserializer has a first data path and a data eye path. The first data path is coupled to a first data out interface of the first serializer-deserializer. A second serializer-deserializer has a second data path. The second data path is coupled to a second data out interface of the second serializer-deserializer. The data eye path of the first serializer-deserializer is coupled to the second data path of the second serializer-deserializer.

Abstract translation: 一种装置一般涉及串行器 - 解串器。 在这种装置中，第一串行器 - 解串器具有第一数据路径和数据眼路径。 第一数据路径耦合到第一串行器 - 解串器的第一数据输出接口。 第二个串行器 - 解串器具有第二数据路径。 第二数据路径耦合到第二串行器 - 解串器的第二数据输出接口。 第一串行器 - 解串器的数据眼路径耦合到第二串行器 - 解串器的第二数据路径。

公开(公告)号：US10419203B1

公开(公告)日：2019-09-17

申请号：US15444002

申请日：2017-02-27

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Antonello Di Fresco

IPC: H04L7/033

Abstract: An example circuit includes: a transmitter configured to transmit a clock pattern based on a transmit clock; a receiver, coupled to the transmitter, configured to sample the clock pattern based on a receive clock to generate a bit pattern, where there is a non-zero frequency difference between the transmit clock and the receive clock; a phase interpolator (PI) configured to add a phase shift to a source clock to supply one of the transmit clock or the receive clock; and a test circuit configured to apply adjustments to the phase shift over a time period and determine a phase distribution of the PI based on changes in the bit pattern over the time period.

公开(公告)号：US10291501B1

公开(公告)日：2019-05-14

申请号：US15886688

申请日：2018-02-01

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Giovanni Guasti

IPC: G11C7/00 ,  H04L12/26 ,  G11C7/10

Abstract: An integrated circuit (IC) includes a first device and a second device. A latency measurement circuit is configured to determine a first latency of the first device; and determine a second latency of the second device based on the first latency.

公开(公告)号：US09143316B1

公开(公告)日：2015-09-22

申请号：US14323680

申请日：2014-07-03

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini

IPC: H03L7/081 ,  H04L7/033 ,  H04L27/233 ,  H04L27/22

CPC classification number: H04L7/0331 ,  H03L7/06 ,  H03L7/081 ,  H04L27/22

Abstract: A data recovery unit includes a phase locked loop configured to receive data samples and generate an output; a first sample selector coupled to the phase locked loop; and an eye scanner coupled to the phase locked loop. The first sample selector is configured to receive the data samples and the output of the phase locked loop. The eye scanner comprises a second sample selector coupled to the phase locked loop via a first horizontal shift module.

Abstract translation: 数据恢复单元包括被配置为接收数据样本并生成输出的锁相环; 耦合到锁相环的第一采样选择器; 以及耦合到锁相环的眼睛扫描器。 第一个采样选择器被配置为接收数据采样和锁相环路的输出。 眼睛扫描仪包括经由第一水平移位模块耦合到锁相环的第二样本选择器。

公开(公告)号：US08666010B1

公开(公告)日：2014-03-04

申请号：US13625100

申请日：2012-09-24

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini

IPC: H04L7/00

CPC classification number: H04L7/02 ,  H03L7/07 ,  H03L2207/06 ,  H04L7/033

Abstract: A bursty phase detector comprises upper and lower branches. The upper branch includes a voltage-controlled oscillator (VCO) providing a VCO phase; a phase detector with a first input for receiving a data stream and a second input coupled to the output of the VCO, the phase detector providing a phase error; a sample selector with a first input for receiving a sum of the VCO phase and the phase error, and a second input coupled to receive the data stream, the sample selector providing a data stream sample; a signal stream detector with a first input for receiving the sum of the VCO phase and the phase error, and a second input coupled to the output of the sample selector, the signal stream detector generating a data stream phase and a data stream detect signal. The lower branch includes a delay component with an input for receiving the data stream.

Abstract translation: 突发相位检测器包括上分支和下分支。 上分支包括提供VCO相位的压控振荡器（VCO）; 具有用于接收数据流的第一输入和耦合到所述VCO的输出的第二输入的相位检测器，所述相位检测器提供相位误差; 具有用于接收VCO相位和相位误差之和的第一输入的采样选择器，以及耦合以接收数据流的第二输入，所述采样选择器提供数据流样本; 具有用于接收VCO相位和相位误差之和的第一输入的信号流检测器，以及耦合到采样选择器的输出端的第二输入，信号流检测器产生数据流相位和数据流检测信号。 下分支包括具有用于接收数据流的输入的延迟分量。

公开(公告)号：US12149348B2

公开(公告)日：2024-11-19

申请号：US17987659

申请日：2022-11-15

Applicant: XILINX, INC.

Inventor： Paolo Novellini

IPC: H04L1/00 ,  H04L7/00 ,  H04L7/033

Abstract: A fast clock domain crossing architecture for high frequency trading includes a receiver that recovers data and a clock of a first clock domain from a communication from an exchange, functional circuitry that generates and a buy/sell command based on the recovered data and the recovered clock, format circuitry that formats the command in a second clock domain, and a transmitter that transmits the formatted command to the exchange. The architecture further includes error detection circuitry that detects bit errors that arise from an asynchronous boundary of the clock domains without increasing a round-trip latency, and/or synchronization circuitry that synchronizes the clock domains, where the synchronization circuitry includes a cleanup PLL that filters input jitter and a phase detector and variable delay line that compensate for latency within the architecture.

公开(公告)号：US11637645B1

公开(公告)日：2023-04-25

申请号：US17026115

申请日：2020-09-18

Applicant: XILINX, INC.

Inventor： Paolo Novellini

IPC: H04J3/06 ,  H04L7/00

Abstract: A method for measuring asynchronous timestamp requests includes receiving a timestamp (“TS”) request from a client device during a first interval of a time of day (“TOD”) clock, and calculating, using the TOD clock, at a next interval of the TOD clock, a TS correction of the TS request relative to a reference point of the first TOD clock interval. The method further includes adding the TS correction to the reference point of the first interval of the TOD clock, and outputting the corrected TS to the client device.