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公开(公告)号：US10790847B1
公开(公告)日：2020-09-29
申请号：US16525982
申请日：2019-07-30
Applicant: Xilinx, Inc.
Inventor： Pedro W. Neto
Abstract: Apparatus and associated methods relate to unit circuits that having a number of capacitors and/or buffers controlled by two different control signals, capacitors and/or buffers that receiving, through routing, a same control signal from a control circuit are physically placed adjacent without crossing routings that connects capacitors and/or buffers controlled by a different control signal. In an illustrative example, a first capacitor may be configured to receive a first control signal through an inverting buffer, and a second capacitor may be configured to receive the first control signal through a non-inverting buffer, the inverting buffer and the non-inverting buffer may be provided by an integrated buffer structure. By arranging the physical positions of the capacitors and/or buffers, wire capacitances of the unit circuit may be advantageously reduced.
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公开(公告)号：US10236901B1
公开(公告)日：2019-03-19
申请号：US15991767
申请日：2018-05-29
Applicant: Xilinx, Inc.
Inventor： Pedro W. Neto
Abstract: A circuit for asynchronous clock generation is described. The circuit comprises a first comparator configured to receive an analog input signal; a second comparator configured to receive the analog input signal; and a clocking circuit coupled to the first comparator and the second comparator; wherein the clocking circuit generates a first asynchronous clock signal for the first comparator and a second asynchronous clock signal for the second comparator. A method of providing asynchronous clock generation is also described.
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Patent Agency Ranking
公开(公告)号：US10763879B1
公开(公告)日：2020-09-01
申请号：US16526000
申请日：2019-07-30
Applicant: Xilinx, Inc.
Inventor： Pedro W. Neto
Abstract: Apparatus and associated methods relate to a clock generation circuit which generates asynchronous clock signals for a successive approximation ADC architecture based on time-interleaved comparators. In an illustrative example, a circuit may include (a) a first comparator configured to receive an input signal and generate a first ready signal to indicate a comparison decision being complete, (b) a second comparator configured to receive the input signal and generate a second ready signal to indicate a comparison decision being complete, and (c) a clock generation circuit coupled to receive the first and the second ready signals and generate a first clock for the first comparator and a second clock for the second comparator. The first and the second clock signals may be in anti-phase. Thus, each comparator may have enough time to reach a valid comparison in each successive approximation cycle, and kickback noises at comparator' inputs may be advantageously reduced.
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公开(公告)号：US20170264467A1
公开(公告)日：2017-09-14
申请号：US15066354
申请日：2016-03-10
Applicant: Xilinx, Inc.
Inventor： Pedro W. Neto
IPC: H04L25/03
CPC classification number: H04L25/03057 , H04L25/0272 , H04L25/0292 , H04L25/03019 , H04L27/01
Abstract: Apparatuses and method relating to DFE include a decision feedback equalizer with first and second integrating summers configured to receive an input differential signal. A bias current circuit is configured to alternate biasing of the first and second integrating summers. The first and second integrating summers alternately integrate, during clock signal phases of a clock signal and its complement, for transconductance of the input differential signal to a first output differential signal and a second output differential signal, respectively. The first and second integrating summers alternately drive, during other clock signal phases of the clock signal and its complement, residual voltages of the first output differential signal and the second output differential signal, respectively, to a same voltage level. A first clock signal and a second clock signal are out of phase with respect to one another for interleaving the first output differential signal and the second output differential signal.
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公开(公告)号：US10911060B1
公开(公告)日：2021-02-02
申请号：US16683854
申请日：2019-11-14
Applicant: Xilinx, Inc.
Inventor： Pedro W. Neto , Ronan Casey , Declan Carey
Abstract: Apparatus and associated methods relate to a time-interleaved integrating sampling front-end circuit using integrating buffers. In an illustrative example, a circuit may include N sampling layers of circuits, an ith sampling layer of circuits of the N sampling layers of circuits may include: (a) Xi buffers configured to receive an analog signal, Xi≥1, and, (b) Yi track-and-hold circuits, each track-and-hold circuit of the Yi track-and-hold circuits is coupled to an output of a corresponding buffer of the X buffers, Yi≥1, at least one buffer of the Xi buffers may include an integrating buffer, N≥i≥1. By implementing integrating buffers, a faster linear type of step settling response may be obtained as opposed to a slower exponential type of settling response.
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公开(公告)号：US10862496B1
公开(公告)日：2020-12-08
申请号：US16525986
申请日：2019-07-30
Applicant: Xilinx, Inc.
Inventor： Pedro W. Neto
Abstract: Apparatus and associated methods relate to a logic circuit having a number of unit circuits performing buffering and data storage functionalities in parallel. In an illustrative example, a logic circuit may include N unit circuits for data storage and N−1 unit circuits for buffering. During a conversion cycle, only an ith unit circuit of the N unit circuits and an (i−1)th unit circuit of the N−1 unit circuits may be enabled. Output status of the ith unit circuit of the N unit circuits may be monitored to disable the ith unit circuit, and also enable an (i−1)th unit circuit of the N unit circuits and an (i−2)th unit circuit of the N−1 unit circuits. By performing buffering and data storage in parallel, propagation delays in the SAR logic circuit may advantageously be reduced, and thus, conversion time of a successive-approximation-register (SAR) analog-to-digital converter (ADC) may be advantageously reduced.
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公开(公告)号：US10069655B2
公开(公告)日：2018-09-04
申请号：US15066354
申请日：2016-03-10
Applicant: Xilinx, Inc.
Inventor： Pedro W. Neto
Abstract: Apparatuses and method relating to DFE include a decision feedback equalizer with first and second integrating summers configured to receive an input differential signal. A bias current circuit is configured to alternate biasing of the first and second integrating summers. The first and second integrating summers alternately integrate, during clock signal phases of a clock signal and its complement, for transconductance of the input differential signal to a first output differential signal and a second output differential signal, respectively. The first and second integrating summers alternately drive, during other clock signal phases of the clock signal and its complement, residual voltages of the first output differential signal and the second output differential signal, respectively, to a same voltage level. A first clock signal and a second clock signal are out of phase with respect to one another for interleaving the first output differential signal and the second output differential signal.
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