公开(公告)号：US09899088B1

公开(公告)日：2018-02-20

申请号：US14862750

申请日：2015-09-23

Applicant: Xilinx, Inc.

Inventor： Weirong Jiang

IPC: G06F12/00 ,  G11C15/04 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/0864

CPC classification number: G11C15/046 ,  G06F3/0626 ,  G06F3/0638 ,  G06F12/0802 ,  G06F12/0864 ,  G11C7/1006 ,  G11C15/00

Abstract: Circuits and methods are disclosed for decomposition of a content addressable memory into a plurality of CAMs having a lower cost. In an example implementation, a set of CAM rules are grouped into a plurality of subsets. For each of the subsets, CAM rules in the subset are reformatted for storage in a respective CAM configured to store fewer ternary bits or configured for prefix match. Each reformatted subset of CAM rules are stored in the respective CAM. A search key formatting circuit is configured to reformat an input search key for each of the respective CAMs is used to store the reformatted subsets to produce a respective reformatted search key and input the respective reformatted search key to the respective CAM.

公开(公告)号：US09110524B1

公开(公告)日：2015-08-18

申请号：US14299736

申请日：2014-06-09

Applicant: Xilinx, Inc.

Inventor： Weirong Jiang ,  Gordon J. Brebner ,  Yi-Hua Yang

IPC: H03K19/173 ,  G06F1/04 ,  G05B19/045

CPC classification number: G06F1/04 ,  G05B19/045 ,  G05B2219/23289 ,  G06F1/10

Abstract: In an FSM circuit, look-ahead-cascade modules are coupled to receive possible states and corresponding subsets of data inputs. Merge modules are coupled to a second-to-the-lowest to highest order of the look-ahead-cascade modules. The second-to-the-lowest to highest order of disambiguation modules are coupled to at least a portion of the merge modules. The lowest order of the disambiguation modules is coupled to the lowest order of the look-ahead-cascade modules. The lowest-to-highest order of the disambiguation modules are coupled to receive respective sets of interim states of rN states each to select respective sets of next states of r states each. A state register is coupled to receive a portion of the highest order of the sets of next states to provide a select signal. Each of the disambiguation modules is coupled to receive the select signal for selection of the sets of next states of the r states each.

Abstract translation: 在FSM电路中，先行级联模块被耦合以接收可能的状态和相应的数据输入子集。 合并模块耦合到先行级联模块的第二到最低级别。 消歧模块的第二到最低到最高顺序耦合到合并模块的至少一部分。 消歧模块的最低顺序与先行级联模块的最低级联联。 消歧模块的最低到最高顺序被耦合以接收各自的rN状态的各个中间状态集合，以各自选择各状态的下一个状态。 状态寄存器被耦合以接收下一状态组的最高阶的一部分以提供选择信号。 每个消歧模块被耦合以接收选择信号，用于选择各状态的下一个状态的集合。

公开(公告)号：US09756154B1

公开(公告)日：2017-09-05

申请号：US14512766

申请日：2014-10-13

Applicant: Xilinx, Inc.

Inventor： Weirong Jiang

IPC: H04L29/08 ,  H04L29/06

CPC classification number: H04L69/324 ,  H04L43/00 ,  H04L43/028 ,  H04L43/0847 ,  H04L69/22

Abstract: A system for processing data includes a filtering module having a plurality of processing units, a state accumulator, and a merging network coupled to the processing units and the state accumulator. Each processing unit is configured to output a set of two sub-state vectors and a packet continuance indicator. The state accumulator is configured to store a state resulted from previous processing cycles by the processing units. The merging network is configured to output a master state vector based at least in part on the set of two sub-state vectors, the stored state, and the packet continuance indicators output from the processing units.

公开(公告)号：US09674081B1

公开(公告)日：2017-06-06

申请号：US14705907

申请日：2015-05-06

Applicant: Xilinx, Inc.

Inventor： Weirong Jiang ,  Gordon J. Brebner

IPC: H04L12/721 ,  H04L12/24 ,  H04L12/741

CPC classification number: H04L45/38 ,  H04L41/0803 ,  H04L45/745

Abstract: Methods and apparatus for using dynamic programming to determine the most efficient mapping of a pipeline of virtual flow tables (VFTs) onto a pipeline of physical flow tables (PFTs) in the data plane of a software-defined networking (SDN) device are described. One example method of determining a configuration for an SDN device generally includes receiving a representation of a series of one or more VFTs, each of the VFTs having one or more properties; receiving a representation of a series of one or more PFTs for hardware of the SDN device, each of the PFTs having one or more capabilities; generating, using dynamic programming based on the properties of the VFTs and the capabilities of the PFTs, a mapping of the series of VFTs onto the series of PFTs; and outputting the generated mapping for implementation on the hardware of the SDN device.

公开(公告)号：US10115463B1

公开(公告)日：2018-10-30

申请号：US14750947

申请日：2015-06-25

Applicant: Xilinx, Inc.

Inventor： Weirong Jiang ,  Denis Rystsov

IPC: G11C15/04 ,  G06F11/07

Abstract: In an example, an integrated circuit (IC) includes a memory including at least one random access memory (RAM). Each of the at least one RAM stores bits representing match vectors indicative of whether search keys match ternary rules. The IC further includes a verification circuit, coupled to the memory, operable to verify the bits stored in the at least one RAM by performing at least one of: decoding at least one of the ternary rules from the bits stored in the at least one RAM; or checking the bits stored in the at least one RAM against expected content of at least one of the ternary rules.

公开(公告)号：US09350385B2

公开(公告)日：2016-05-24

申请号：US13841574

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Weirong Jiang ,  Gordon J. Brebner ,  Mark B. Carson

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/09

CPC classification number: H03M13/09 ,  H03M13/091

Abstract: Devices and methods for performing a cyclic redundancy check are disclosed. For example, a device has a splitter for splitting a data word into a plurality of paths. The device also has a plurality of cyclic redundancy check units. Each of the units is for processing a respective one of the paths. In addition, each of the units includes a first output port for outputting a cyclic redundancy check value for a packet ending within the unit and a second output port for outputting a cyclic redundancy check value for a packet starting or ongoing within the unit.

Abstract translation: 公开了用于执行循环冗余校验的设备和方法。 例如，设备具有用于将数据字分割成多个路径的分离器。 该设备还具有多个循环冗余校验单元。 每个单元用于处理相应的一个路径。 另外，每个单元包括用于输出用于在单元内结束的分组的循环冗余校验值的第一输出端口和用于输出在单元内开始或正在进行的分组的循环冗余校验值的第二输出端口。

公开(公告)号：US09111615B1

公开(公告)日：2015-08-18

申请号：US14043679

申请日：2013-10-01

Applicant: Xilinx, Inc.

Inventor： Weirong Jiang

IPC: G11C15/00 ,  G11C15/04 ,  G06F17/30

CPC classification number: G11C15/04 ,  G06F17/30982

Abstract: A memory is disclosed that includes one or more TCAM memory units, each configured to store a respective set of rules. Each unit has an input coupled to receive an input search key from an input of the memory and includes a plurality of stages 1 through H. Each stage is configured to receive a respective multi-bit segment of the input search key and provide a result segment in response thereto. The result segment includes, for each rule of the respective set of rules, a bit that indicates whether or not the rule matches the segment of the input search key. Each unit also includes a first output circuit configured to generate a combined result indicating which rules match all of the respective segments received by each of the plurality of stages. The memory can also include one or more update circuits to update rules in a plurality of units.

Abstract translation: 公开了一种存储器，其包括一个或多个TCAM存储器单元，每个TCAM存储器单元被配置为存储相应的一组规则。 每个单元具有耦合以从存储器的输入接收输入搜索关键字的输入，并且包括多个级1至H.每一级被配置为接收输入搜索关键字的相应多位段并提供结果段 作为响应。 对于各组规则的每个规则，结果段包括指示规则是否与输入搜索关键字的段匹配的位。 每个单元还包括第一输出电路，其被配置为生成指示哪些规则与由多个级中的每一个接收的各个段相匹配的组合结果。 存储器还可以包括用于更新多个单元中的规则的一个或多个更新电路。

公开(公告)号：US20140281844A1

公开(公告)日：2014-09-18

申请号：US13841574

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Weirong Jiang ,  Gordon J. Brebner ,  Mark B. Carson

IPC: H03M13/09

CPC classification number: H03M13/09 ,  H03M13/091

Abstract: Devices and methods for performing a cyclic redundancy check are disclosed. For example, a device has a splitter for splitting a data word into a plurality of paths. The device also has a plurality of cyclic redundancy check units. Each of the units is for processing a respective one of the paths. In addition, each of the units includes a first output port for outputting a cyclic redundancy check value for a packet ending within the unit and a second output port for outputting a cyclic redundancy check value for a packet starting or ongoing within the unit.

Abstract translation: 公开了用于执行循环冗余校验的设备和方法。 例如，设备具有用于将数据字分割成多个路径的分离器。 该设备还具有多个循环冗余校验单元。 每个单元用于处理相应的一个路径。 另外，每个单元包括用于输出用于在单元内结束的分组的循环冗余校验值的第一输出端口和用于输出在单元内开始或正在进行的分组的循环冗余校验值的第二输出端口。