公开(公告)号：US20110316073A1

公开(公告)日：2011-12-29

申请号：US13254041

申请日：2010-12-15

申请人： Xinxong Cheng ,  Dawei He ,  Zhongjian Wang ,  Dawei Xu ,  Chao Xia ,  Zhaorui Song ,  Yuehui Yu

发明人： Xinxong Cheng ,  Dawei He ,  Zhongjian Wang ,  Dawei Xu ,  Chao Xia ,  Zhaorui Song ,  Yuehui Yu

IPC分类号： H01L27/12

CPC分类号： H01L27/1211 ,  H01L21/845

摘要： The present invention discloses an SOI CMOS device having a vertical gate structure, comprising: an SOI substrate, and an NMOS region and a PMOS region grown on the SOI substrate, wherein the NMOS region and the PMOS region share one vertical gate region, said vertical gate region lying in the same plane as the NMOS region and the PMOS region and between the NMOS region and the PMOS region; a gate oxide layer is arranged between the vertical gate region and the NMOS region for isolation; and a gate oxide layer is arranged between the vertical gate region and the PMOS region for isolation. The present invention occupies small area, contains less pattern layers, requires a simple process, has an open body region that can completely avoid the floating effect of the traditional SOI CMOS device, and is convenient to parasitic resistance and capacitance tests.

摘要翻译： 本发明公开了一种具有垂直栅极结构的SOI CMOS器件，包括：SOI衬底，以及在SOI衬底上生长的NMOS区域和PMOS区域，其中NMOS区域和PMOS区域共享一个垂直栅极区域，所述垂直 栅极区域位于与NMOS区域和PMOS区域在NMOS区域和PMOS区域相同的平面中; 在垂直栅极区域和NMOS区域之间布置栅极氧化层用于隔离; 并且栅极氧化物层被布置在垂直栅极区域和PMOS区域之间用于隔离。 本发明占地面积小，包含较少的图案层，需要简单的工艺，具有开放的体区，可以完全避免传统SOI CMOS器件的浮动效应，方便寄生电阻和电容测试。

公开(公告)号：US08354330B2

公开(公告)日：2013-01-15

申请号：US13203724

申请日：2010-12-15

申请人： Xinhong Cheng ,  Dawei He ,  Zhongjian Wang ,  Dawei Xu ,  Chao Xia ,  Zhaorui Song ,  Yuehui Yu

发明人： Xinhong Cheng ,  Dawei He ,  Zhongjian Wang ,  Dawei Xu ,  Chao Xia ,  Zhaorui Song ,  Yuehui Yu

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L29/7824 ,  H01L21/76283 ,  H01L29/0634 ,  H01L29/423 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835 ,  H01L29/78603

摘要： The present invention relates to a method of fabricating an SOI SJ LDMOS structure that can completely eliminate the substrate-assisted depletion effects, comprising the following steps: step one: a conducting layer is prepared below the SOI BOX layer using the bonding technique; the conducting layer is prepared in the following way: depositing a barrier layer on a first bulk silicon wafer, and then depositing a charge conducting layer, thereby obtaining a first intermediate structure; forming a silicon dioxide layer on a second bulk silicon wafer via thermal oxidation, then depositing a barrier layer, and finally depositing a charge conducting layer, thereby obtaining a second intermediate structure; bonding the first intermediate structure and the second intermediate structure using the metal bonding technology to arrange the conducting layer below the SOI BOX layer; step two: a SJ LDMOS structure is fabricated on the SOI substrate having a conducting layer. The present invention is capable of releasing the charge accumulated at the lower interface of the BOX layer, eliminating the effect of the vertical charge on the charge balance between the p-type pillar and the n-type pillar, and therefore completely eliminating the substrate-assisted depletion effects and elevating the breakdown voltage of the device.

摘要翻译： 本发明涉及一种制造能够完全消除衬底辅助耗尽效应的SOI SJ LDMOS结构的方法，包括以下步骤：第一步：使用接合技术在SOI BOX层下制备导电层; 以下列方式制备导电层：在第一体硅晶片上沉积阻挡层，然后沉积电荷导电层，从而获得第一中间结构; 通过热氧化在第二体硅晶片上形成二氧化硅层，然后沉积阻挡层，最后沉积电荷导电层，从而获得第二中间结构; 使用金属接合技术接合第一中间结构和第二中间结构以将导电层布置在SOI BOX层下方; 第二步：在具有导电层的SOI衬底上制造SJLDMOS结构。 本发明能够释放在BOX层的下界面积聚的电荷，消除了垂直电荷对p型柱和n型柱之间的电荷平衡的影响，因此完全消除了基板 - 辅助耗尽效应和升高器件的击穿电压。

公开(公告)号：US20120273861A1

公开(公告)日：2012-11-01

申请号：US13256435

申请日：2011-06-08

申请人： Xinhong Cheng ,  Dawei Xu ,  Zhongjian Wang ,  Chao Xia ,  Dawei He ,  Zhaorui Song ,  Yuehui Yu

发明人： Xinhong Cheng ,  Dawei Xu ,  Zhongjian Wang ,  Chao Xia ,  Dawei He ,  Zhaorui Song ,  Yuehui Yu

IPC分类号： H01L29/94 ,  H01L21/334 ,  H01L21/3105

CPC分类号： H01L28/40 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention relates to a method of depositing a gate dielectric, a method of preparing a MIS capacitor and the MIS capacitor. In the method of depositing the gate dielectric, a semiconductor substrate surface is preprocessed with oxygen plasma and nitrogen-containing plasma to form a nitrogen-containing oxide layer thereon. Then, a high-k gate dielectric layer is grown on the nitrogen-containing oxide layer surface by a plasma-enhanced atomic layer deposition process, and the oxide layer converts during the gate dielectric layer growth process into a buffer layer of a dielectric constant higher than SiO2. Then, a metal electrode is formed on both an upper layer and a lower layer of the thus-formed semiconductor construction, so that a MIS capacitor is prepared. According to the present invention, the formation of the buffer layer enables the interface characteristics between semiconductor materials and high-k gate dielectric layers to be improved effectively, equivalent oxide thickness (EOT) to be reduced and electrical properties to be enhanced.

摘要翻译： 本发明涉及沉积栅极电介质的方法，制备MIS电容器和MIS电容器的方法。 在沉积栅极电介质的方法中，半导体衬底表面用氧等离子体和含氮等离子体进行预处理，以在其上形成含氮氧化物层。 然后，通过等离子体增强原子层沉积工艺在含氮氧化物层表面上生长高k栅极电介质层，并且氧化物层在栅极介电层生长过程中转换成介电常数较高的缓冲层 比SiO 2。 然后，在如此形成的半导体结构的上层和下层上形成金属电极，从而制备MIS电容器。 根据本发明，缓冲层的形成能够有效地提高半导体材料与高k栅介质层之间的界面特性，减小等效氧化物厚度（EOT），提高电性能。