公开(公告)号：US08354330B2

公开(公告)日：2013-01-15

申请号：US13203724

申请日：2010-12-15

申请人： Xinhong Cheng ,  Dawei He ,  Zhongjian Wang ,  Dawei Xu ,  Chao Xia ,  Zhaorui Song ,  Yuehui Yu

发明人： Xinhong Cheng ,  Dawei He ,  Zhongjian Wang ,  Dawei Xu ,  Chao Xia ,  Zhaorui Song ,  Yuehui Yu

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L29/7824 ,  H01L21/76283 ,  H01L29/0634 ,  H01L29/423 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835 ,  H01L29/78603

摘要： The present invention relates to a method of fabricating an SOI SJ LDMOS structure that can completely eliminate the substrate-assisted depletion effects, comprising the following steps: step one: a conducting layer is prepared below the SOI BOX layer using the bonding technique; the conducting layer is prepared in the following way: depositing a barrier layer on a first bulk silicon wafer, and then depositing a charge conducting layer, thereby obtaining a first intermediate structure; forming a silicon dioxide layer on a second bulk silicon wafer via thermal oxidation, then depositing a barrier layer, and finally depositing a charge conducting layer, thereby obtaining a second intermediate structure; bonding the first intermediate structure and the second intermediate structure using the metal bonding technology to arrange the conducting layer below the SOI BOX layer; step two: a SJ LDMOS structure is fabricated on the SOI substrate having a conducting layer. The present invention is capable of releasing the charge accumulated at the lower interface of the BOX layer, eliminating the effect of the vertical charge on the charge balance between the p-type pillar and the n-type pillar, and therefore completely eliminating the substrate-assisted depletion effects and elevating the breakdown voltage of the device.

摘要翻译： 本发明涉及一种制造能够完全消除衬底辅助耗尽效应的SOI SJ LDMOS结构的方法，包括以下步骤：第一步：使用接合技术在SOI BOX层下制备导电层; 以下列方式制备导电层：在第一体硅晶片上沉积阻挡层，然后沉积电荷导电层，从而获得第一中间结构; 通过热氧化在第二体硅晶片上形成二氧化硅层，然后沉积阻挡层，最后沉积电荷导电层，从而获得第二中间结构; 使用金属接合技术接合第一中间结构和第二中间结构以将导电层布置在SOI BOX层下方; 第二步：在具有导电层的SOI衬底上制造SJLDMOS结构。 本发明能够释放在BOX层的下界面积聚的电荷，消除了垂直电荷对p型柱和n型柱之间的电荷平衡的影响，因此完全消除了基板 - 辅助耗尽效应和升高器件的击穿电压。

公开(公告)号：US20120276718A1

公开(公告)日：2012-11-01

申请号：US13145033

申请日：2011-06-08

申请人： Xinhong Cheng ,  Youwei Zhang ,  Dawei Xu ,  Zhongjian Wang ,  Chao Xia ,  Dawei He ,  Yuehui Yu

发明人： Xinhong Cheng ,  Youwei Zhang ,  Dawei Xu ,  Zhongjian Wang ,  Chao Xia ,  Dawei He ,  Yuehui Yu

IPC分类号： H01L21/283

CPC分类号： H01L21/28194 ,  H01L29/1606 ,  H01L29/513 ,  H01L29/517

摘要： The present invention provides a method of fabricating a graphene-based field effect transistor, which includes steps of: providing a semiconductor substrate on which a non-functionized graphene layer is formed; forming a metal oxide film as a nucleation layer through a reaction between a metal source and water which acts as oxidizer and is physically absorbed to a surface of the graphene layer; and generating a HfO2 gate dielectric layer through a reaction between a hafnium source and water acting as oxidizer by using the nucealtion layer. In comparison with the prior art, the method of the present invention is mainly characterized in that the metal oxide film acting as the nucleation layer is formed through a reaction between the metal source and water which acts as oxidizer and is physically absorbed to the surface of graphene. This enables a HfO2 gate dielectric film to be prepared later on with an atomic layer deposition process to have good uniformity, a high coverage rate, and a high quality and prevents the defects which may degrade the performance of the graphene-based field effect transistor from entering the crystal lattice of graphene.

摘要翻译： 本发明提供了一种制造基于石墨烯的场效应晶体管的方法，其包括以下步骤：提供其上形成有非功能化石墨烯层的半导体衬底; 通过金属源和作为氧化剂的水之间的反应形成金属氧化物膜作为成核层，并被物理吸收到石墨烯层的表面; 以及通过铪源和作为氧化剂的水之间的反应，通过使用该反应层产生HfO 2栅极介电层。 与现有技术相比，本发明的方法的主要特征在于，作为成核层的金属氧化物膜是通过金属源和作为氧化剂的水之间的反应形成的，并且物理上被吸收到 石墨烯 这使得以后的原子层沉积工艺能够制备HfO 2栅极电介质膜以具有良好的均匀性，高覆盖率和高质量，并且防止可能降低基于石墨烯的场效应晶体管的性能的缺陷 进入石墨烯的晶格。

公开(公告)号：US20120273861A1

公开(公告)日：2012-11-01

申请号：US13256435

申请日：2011-06-08

申请人： Xinhong Cheng ,  Dawei Xu ,  Zhongjian Wang ,  Chao Xia ,  Dawei He ,  Zhaorui Song ,  Yuehui Yu

发明人： Xinhong Cheng ,  Dawei Xu ,  Zhongjian Wang ,  Chao Xia ,  Dawei He ,  Zhaorui Song ,  Yuehui Yu

IPC分类号： H01L29/94 ,  H01L21/334 ,  H01L21/3105

CPC分类号： H01L28/40 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention relates to a method of depositing a gate dielectric, a method of preparing a MIS capacitor and the MIS capacitor. In the method of depositing the gate dielectric, a semiconductor substrate surface is preprocessed with oxygen plasma and nitrogen-containing plasma to form a nitrogen-containing oxide layer thereon. Then, a high-k gate dielectric layer is grown on the nitrogen-containing oxide layer surface by a plasma-enhanced atomic layer deposition process, and the oxide layer converts during the gate dielectric layer growth process into a buffer layer of a dielectric constant higher than SiO2. Then, a metal electrode is formed on both an upper layer and a lower layer of the thus-formed semiconductor construction, so that a MIS capacitor is prepared. According to the present invention, the formation of the buffer layer enables the interface characteristics between semiconductor materials and high-k gate dielectric layers to be improved effectively, equivalent oxide thickness (EOT) to be reduced and electrical properties to be enhanced.

摘要翻译： 本发明涉及沉积栅极电介质的方法，制备MIS电容器和MIS电容器的方法。 在沉积栅极电介质的方法中，半导体衬底表面用氧等离子体和含氮等离子体进行预处理，以在其上形成含氮氧化物层。 然后，通过等离子体增强原子层沉积工艺在含氮氧化物层表面上生长高k栅极电介质层，并且氧化物层在栅极介电层生长过程中转换成介电常数较高的缓冲层 比SiO 2。 然后，在如此形成的半导体结构的上层和下层上形成金属电极，从而制备MIS电容器。 根据本发明，缓冲层的形成能够有效地提高半导体材料与高k栅介质层之间的界面特性，减小等效氧化物厚度（EOT），提高电性能。

公开(公告)号：US20120021569A1

公开(公告)日：2012-01-26

申请号：US13133871

申请日：2010-09-07

申请人： Xinhong Cheng ,  Zhongjian Wang ,  Yuehui Yu ,  Dawei He ,  Dawei Xu ,  Chao Xia

发明人： Xinhong Cheng ,  Zhongjian Wang ,  Yuehui Yu ,  Dawei He ,  Dawei Xu ,  Chao Xia

IPC分类号： H01L21/331 ,  H01L21/336

CPC分类号： H01L29/7824 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/42368 ,  H01L29/66681

摘要： The present invention relates to a manufacturing method of SOI devices, and in particular, to a manufacturing method of SOI high-voltage power devices. The method comprises steps of: forming a first oxide layer in a section on the surface of the SOI substrate; removing the first oxide layer to form a depressed area in the corresponding section of the upper surface of the SOI substrate; forming a second oxide layer, the upper surface of which is as high as the that of the SOI substrate, in the depressed area formed in step (B); performing photoetching and doping processes to form a P-type region, an N-type region and a gate region on the thus-formed structure where the second oxide layer is formed; forming a third oxide layer by deposition on the drift region of the structure after P-type and N-type regions are formed; wherein the total thickness of the third oxide layer and the second oxide layer approximates to the thickness of the buried oxide layer in the SOI substrate; and forming metal sub-regions, which are respectively in contact with the P-type region, the N-type region and the gate region, on the structure where the third oxide layer is formed, thereby forming a high-voltage power device.

摘要翻译： 本发明涉及SOI器件的制造方法，特别涉及SOI高压电力器件的制造方法。 该方法包括以下步骤：在SOI衬底的表面上的部分中形成第一氧化物层; 去除第一氧化物层以在SOI衬底的上表面的相应部分中形成凹陷区域; 在步骤（B）中形成的凹陷区域形成其上表面与SOI衬底的上表面的第二氧化物层; 进行光刻和掺杂工艺以在形成第二氧化物层的如此形成的结构上形成P型区域，N型区域和栅极区域; 在形成P型和N型区域之后，通过沉积在所述结构的漂移区上形成第三氧化物层; 其中所述第三氧化物层和所述第二氧化物层的总厚度接近所述SOI衬底中所述掩埋氧化物层的厚度; 并且在形成第三氧化物层的结构上形成分别与P型区域，N型区域和栅极区域接触的金属子区域，从而形成高压电力装置。

公开(公告)号：US20110316073A1

公开(公告)日：2011-12-29

申请号：US13254041

申请日：2010-12-15

申请人： Xinxong Cheng ,  Dawei He ,  Zhongjian Wang ,  Dawei Xu ,  Chao Xia ,  Zhaorui Song ,  Yuehui Yu

发明人： Xinxong Cheng ,  Dawei He ,  Zhongjian Wang ,  Dawei Xu ,  Chao Xia ,  Zhaorui Song ,  Yuehui Yu

IPC分类号： H01L27/12

CPC分类号： H01L27/1211 ,  H01L21/845

摘要： The present invention discloses an SOI CMOS device having a vertical gate structure, comprising: an SOI substrate, and an NMOS region and a PMOS region grown on the SOI substrate, wherein the NMOS region and the PMOS region share one vertical gate region, said vertical gate region lying in the same plane as the NMOS region and the PMOS region and between the NMOS region and the PMOS region; a gate oxide layer is arranged between the vertical gate region and the NMOS region for isolation; and a gate oxide layer is arranged between the vertical gate region and the PMOS region for isolation. The present invention occupies small area, contains less pattern layers, requires a simple process, has an open body region that can completely avoid the floating effect of the traditional SOI CMOS device, and is convenient to parasitic resistance and capacitance tests.

摘要翻译： 本发明公开了一种具有垂直栅极结构的SOI CMOS器件，包括：SOI衬底，以及在SOI衬底上生长的NMOS区域和PMOS区域，其中NMOS区域和PMOS区域共享一个垂直栅极区域，所述垂直 栅极区域位于与NMOS区域和PMOS区域在NMOS区域和PMOS区域相同的平面中; 在垂直栅极区域和NMOS区域之间布置栅极氧化层用于隔离; 并且栅极氧化物层被布置在垂直栅极区域和PMOS区域之间用于隔离。 本发明占地面积小，包含较少的图案层，需要简单的工艺，具有开放的体区，可以完全避免传统SOI CMOS器件的浮动效应，方便寄生电阻和电容测试。

公开(公告)号：US08377755B2

公开(公告)日：2013-02-19

申请号：US13133886

申请日：2010-09-07

申请人： Xinhong Cheng ,  Zhongjian Wang ,  Yuehui Yu ,  Dawei He ,  Dawei Xu ,  Chao Xia

发明人： Xinhong Cheng ,  Zhongjian Wang ,  Yuehui Yu ,  Dawei He ,  Dawei Xu ,  Chao Xia

IPC分类号： H01L21/332

CPC分类号： H01L29/7824 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/66681

摘要： A method of manufacturing a SOI high voltage power chip with trenches is disclosed. The method comprises: forming a cave and trenches at a SOI substrate; filling oxide in the cave; oxidizing the trenches, forming oxide isolation regions for separating low voltage devices at the same time; filling oxide in the oxidized trenches; and then forming drain regions, source regions and gate regions for a high voltage power device and low voltage devices. The process involves depositing an oxide layer overlapping the cave of the SOI substrate. A SOI high voltage power chip thus made will withstand at least above 700V voltage.

摘要翻译： 公开了一种制造具有沟槽的SOI高电压功率芯片的方法。 该方法包括：在SOI衬底上形成一个洞和沟槽; 在洞里填充氧化物; 氧化沟槽，形成用于同时分离低压器件的氧化物隔离区; 在氧化沟中填充氧化物; 然后形成用于高压功率器件和低电压器件的漏极区域，源极区域和栅极区域。 该方法包括沉积与SOI衬底的洞重叠的氧化物层。 如此制造的SOI高压功率芯片将承受至少高于700V的电压。

公开(公告)号：US20120058608A1

公开(公告)日：2012-03-08

申请号：US13203724

申请日：2010-12-15

申请人： Xinhong Cheng ,  Dawei He ,  Zhongjian Wang ,  Dawei Xu ,  Chao Xia ,  Zhaorui Son ,  Yuehui Yu

发明人： Xinhong Cheng ,  Dawei He ,  Zhongjian Wang ,  Dawei Xu ,  Chao Xia ,  Zhaorui Son ,  Yuehui Yu

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L29/7824 ,  H01L21/76283 ,  H01L29/0634 ,  H01L29/423 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835 ,  H01L29/78603

摘要： The present invention relates to a method of fabricating an SOI SJ LDMOS structure that can completely eliminate the substrate-assisted depletion effects, comprising the following steps: step one: a conducting layer is prepared below the SOI BOX layer using the bonding technique; the conducting layer is prepared in the following way: depositing a barrier layer on a first bulk silicon wafer, and then depositing a charge conducting layer, thereby obtaining a first intermediate structure; forming a silicon dioxide layer on a second bulk silicon wafer via thermal oxidation, then depositing a barrier layer, and finally depositing a charge conducting layer, thereby obtaining a second intermediate structure; bonding the first intermediate structure and the second intermediate structure using the metal bonding technology to arrange the conducting layer below the SOI BOX layer; step two: a SJ LDMOS structure is fabricated on the SOI substrate having a conducting layer. The present invention is capable of releasing the charge accumulated at the lower interface of the BOX layer, eliminating the effect of the vertical charge on the charge balance between the p-type pillar and the n-type pillar, and therefore completely eliminating the substrate-assisted depletion effects and elevating the breakdown voltage of the device.

摘要翻译： 本发明涉及一种制造能够完全消除衬底辅助耗尽效应的SOI SJ LDMOS结构的方法，包括以下步骤：第一步：使用接合技术在SOI BOX层下制备导电层; 以下列方式制备导电层：在第一体硅晶片上沉积阻挡层，然后沉积电荷导电层，从而获得第一中间结构; 通过热氧化在第二体硅晶片上形成二氧化硅层，然后沉积阻挡层，最后沉积电荷导电层，从而获得第二中间结构; 使用金属接合技术接合第一中间结构和第二中间结构以将导电层布置在SOI BOX层下方; 第二步：在具有导电层的SOI衬底上制造SJLDMOS结构。 本发明能够释放在BOX层的下界面积聚的电荷，消除了垂直电荷对p型柱和n型柱之间的电荷平衡的影响，因此完全消除了基板 - 辅助耗尽效应和升高器件的击穿电压。

公开(公告)号：US07761301B2

公开(公告)日：2010-07-20

申请号：US11583969

申请日：2006-10-20

申请人： Dawei Xu

发明人： Dawei Xu

IPC分类号： G10L13/08 ,  G10L13/00 ,  G06F17/20 ,  G06F17/27

CPC分类号： G10L13/10

摘要： A prosodic control rule generation method includes dividing an input text into language units, estimating a punctuation mark incidence at a boundary between language units in the input text, the punctuation mark incidence indicating a degree that a punctuation mark occurs at the boundary, based on attribute information items of a plurality of language units adjacent to the boundary, and generating a prosodic control rule for speech synthesis including a condition for the punctuation mark incidence based on a plurality of learning data items each concerning prosody and including the punctuation mark incidence.

摘要翻译： 韵律控制规则生成方法包括将输入文本划分为语言单元，估计在输入文本中的语言单元之间的边界处的标点符号入射，基于属性的标点符号入射指示标点标记在边界处发生的程度 与所述边界相邻的多个语言单元的信息项，并且基于多个学习数据项生成用于语音合成的韵律控制规则，所述韵律控制规则包括用于所述标点符号发生的条件，每个所述学习数据项涉及韵律并包括所述标点符号入射。

公开(公告)号：US07408009B2

公开(公告)日：2008-08-05

申请号：US10533625

申请日：2003-11-03

申请人： George W. Roberts ,  Dawei Xu ,  Douglas J. Kiserow ,  Ruben G. Carbonell

发明人： George W. Roberts ,  Dawei Xu ,  Douglas J. Kiserow ,  Ruben G. Carbonell

IPC分类号： C08C19/02 ,  C08F8/04

CPC分类号： C08F8/04 ,  Y02P20/544

摘要： A method of hydrogenating a polymer comprises: (a) providing a dense phase, the dense phase comprising a polymer in a solvent; (b) providing a catalyst system, the catalyst system comprising as least one metal hydrogenation catalyst (preferably including nickel or ruthenium); and (c) providing a light phase, the light phase comprising, consisting of or consisting essentially of hydrogen and carbon dioxide; and (d) contacting the dense phase, the light phase and the catalyst system under conditions in which the hydrogen reacts with the polymer and hydrogenates the polymer.

摘要翻译： 氢化聚合物的方法包括：（a）提供致密相，所述致密相在溶剂中包含聚合物; （b）提供催化剂体系，所述催化剂体系包含至少一种金属氢化催化剂（优选包括镍或钌）; 和（c）提供轻相，所述轻相包含由氢和二氧化碳组成或基本上由氢和二氧化碳组成; 和（d）在氢与聚合物反应并氢化聚合物的条件下使密相，轻相和催化剂体系接触。

公开(公告)号：US08460976B2

公开(公告)日：2013-06-11

申请号：US13133871

申请日：2010-09-07

申请人： Xinhong Cheng ,  Zhongjian Wang ,  Yuehui Yu ,  Dawei He ,  Dawei Xu ,  Chao Xia

发明人： Xinhong Cheng ,  Zhongjian Wang ,  Yuehui Yu ,  Dawei He ,  Dawei Xu ,  Chao Xia

IPC分类号： H01L21/332

CPC分类号： H01L29/7824 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/42368 ,  H01L29/66681

摘要： The present invention relates to a manufacturing method of SOI devices, and in particular, to a manufacturing method of SOI high-voltage power devices. The method comprises steps of: forming a first oxide layer in a section on the surface of the SOI substrate; removing the first oxide layer to form a depressed area in the corresponding section of the upper surface of the SOI substrate; forming a second oxide layer, the upper surface of which is as high as the that of the SOI substrate, in the depressed area formed in step (B); performing photoetching and doping processes to form a P-type region, an N-type region and a gate region on the thus-formed structure where the second oxide layer is formed; forming a third oxide layer by deposition on the drift region of the structure after P-type and N-type regions are formed; wherein the total thickness of the third oxide layer and the second oxide layer approximates to the thickness of the buried oxide layer in the SOI substrate; and forming metal sub-regions, which are respectively in contact with the P-type region, the N-type region and the gate region, on the structure where the third oxide layer is formed, thereby forming a high-voltage power device.

摘要翻译： 本发明涉及SOI器件的制造方法，特别涉及SOI高压电力器件的制造方法。 该方法包括以下步骤：在SOI衬底的表面上的部分中形成第一氧化物层; 去除第一氧化物层以在SOI衬底的上表面的相应部分中形成凹陷区域; 在步骤（B）中形成的凹陷区域形成其上表面与SOI衬底的上表面的第二氧化物层; 进行光刻和掺杂工艺以在形成第二氧化物层的如此形成的结构上形成P型区域，N型区域和栅极区域; 在形成P型和N型区域之后，通过沉积在所述结构的漂移区上形成第三氧化物层; 其中所述第三氧化物层和所述第二氧化物层的总厚度接近所述SOI衬底中所述掩埋氧化物层的厚度; 并且在形成第三氧化物层的结构上形成分别与P型区域，N型区域和栅极区域接触的金属子区域，从而形成高压电力装置。