公开(公告)号：US07492815B2

公开(公告)日：2009-02-17

申请号：US10997397

申请日：2004-11-24

申请人： Yuanbin Guo ,  Jianzhong Zhang ,  Dennis McCain ,  Joseph R. Cavallaro

发明人： Yuanbin Guo ,  Jianzhong Zhang ,  Dennis McCain ,  Joseph R. Cavallaro

IPC分类号： H04B1/707 ,  H03H7/30

CPC分类号： H04L25/03038 ,  H04B1/71055 ,  H04L25/0204 ,  H04L25/021 ,  H04L25/0242 ,  H04L25/0328 ,  H04L2025/03375 ,  H04L2025/03426 ,  H04L2025/03477 ,  H04L2025/03605

摘要： Disclosed is a LMMSE receiver that restores orthogonality of spreading codes in the downlink channel for a spread spectrum signal received over N receive antennas. The FFT-based chip equalizer tap solver reduces the direct matrix inverse of the prior art to the inverse of some submatrices of size N×N with the dimension of the receive antennas, and most efficiently reduces matrix inverses to no larger than 2×2. Complexity is further reduced over a conventional Fast Fourier Transform approach by Hermitian optimization to the inverse of submatrices and tree pruning. For a receiver with N=4 or N=2 with double oversampling, the resulting 4×4 matrices are partitioned into 2×2 block sub-matrices, inverted, and rebuilt into a 4×4 matrix. Common computations are found and repeated computations are eliminated to improve efficiency. Generic design architecture is derived from the special design blocks to eliminate redundancies in complex operations. Optimally, the architecture is parallel and pipelined.

摘要翻译： 公开了一种用于在N个接收天线上接收的扩频信号的下行链路信道中恢复扩频码的正交性的LMMSE接收机。 基于FFT的码片均衡器抽头解算器将现有技术的直接矩阵逆减少为具有接收天线的尺寸的尺寸为N×N的一些子矩阵的倒数，并且最有效地将矩阵反转减小到不大于2×2。 通过Hermitian优化，传统的快速傅立叶变换方法，复杂度进一步降低到子矩阵和树剪枝的倒数。 对于具有N = 4或N = 2的具有双重过采样的接收机，所得到的4×4矩阵被划分为2x2块子矩阵，被反转并重建为4×4矩阵。 发现常规计算，消除重复计算以提高效率。 通用设计架构源于特殊的设计模块，以消除复杂操作中的冗余。 最佳的架构是并行和流水线的。

公开(公告)号：US07706430B2

公开(公告)日：2010-04-27

申请号：US11067498

申请日：2005-02-25

申请人： Yuanbin Guo ,  Dennis McCain ,  Joseph R. Cavallaro

发明人： Yuanbin Guo ,  Dennis McCain ,  Joseph R. Cavallaro

IPC分类号： H04L27/06

CPC分类号： H04B1/71075 ,  H04B2001/71077 ,  H04B2201/70707

摘要： A system, apparatus and method for a multi-stage Parallel Residue Compensation (PRC) receiver for enhanced suppression of the Multiple Access Interference (MAI) in Code Division Multiple Access (CDMA) systems. The accuracy of the interference estimation is improved with a set of weights computed from an adaptive Normalized Least Mean Square (NLMS) algorithm. In order to reduce complexity, the commonality of the multi-code processing is extracted and used to derive a structure of PRC to avoid direct interference cancellation. The derived PRC structure reduces the interference cancellation architecture from a complexity that is proportional to the square of the number of users to a complexity that is linear with respect to the number of users. The complexity is further reduced by replacing dedicated multiplier circuits with simple combinational logic.

摘要翻译： 一种用于增强抑制码分多址（CDMA）系统中的多址干扰（MAI）的多级并行残差补偿（PRC）接收机的系统，装置和方法。 通过从自适应归一化最小二乘法（NLMS）算法计算的一组权重，改善了干扰估计的准确性。 为了降低复杂度，提取多码处理的通用性，并用于导出PRC的结构，以避免直接干扰消除。 导出的PRC结构从与用户数量的平方成正比于与用户数量相关的复杂度的复杂度降低了干扰消除架构。 通过用简单的组合逻辑替换专用乘法电路，进一步降低了复杂度。

公开(公告)号：US08767849B2

公开(公告)日：2014-07-01

申请号：US13405134

申请日：2012-02-24

申请人： Bei Yin ,  Kiarash Amiri ,  Joseph R. Cavallaro ,  Yuanbin Guo

发明人： Bei Yin ,  Kiarash Amiri ,  Joseph R. Cavallaro ,  Yuanbin Guo

IPC分类号： H04K1/10 ,  H04L27/28 ,  H04L25/03 ,  H04J11/00 ,  H04B1/7107

CPC分类号： H04J11/004 ,  H04B1/71072 ,  H04L25/03159

摘要： A wireless receiver is constructed to equalize a time-domain received signal, detect a plurality of symbols of the equalized time-domain received signal, and perform interference cancellation on the time-domain received signal. The interference cancellation can be performed using a partial result produced by an IDFT, and may use only neighboring symbols in a detected plurality of symbols. The resulting wireless receiver can be constructed to operate efficiently under a plurality of wireless standards.

摘要翻译： 构造无线接收机以均衡时域接收信号，检测均衡的时域接收信号的多个符号，并对时域接收信号执行干扰消除。 可以使用由IDFT产生的部分结果来执行干扰消除，并且可以仅使用检测到的多个符号中的相邻符号。 所得到的无线接收机可被构造成在多种无线标准下有效地工作。

公开(公告)号：US08621160B2

公开(公告)日：2013-12-31

申请号：US13329065

申请日：2011-12-16

申请人： Guohui Wang ,  Yang Sun ,  Joseph R. Cavallaro ,  Yuanbin Guo

发明人： Guohui Wang ,  Yang Sun ,  Joseph R. Cavallaro ,  Yuanbin Guo

IPC分类号： G06F12/06 ,  G06F13/376

CPC分类号： H03M13/2957 ,  H03M13/395 ,  H03M13/3972 ,  H03M13/6561 ,  H03M13/6566

摘要： A memory control unit of a turbo code decoder includes a buffer having a plurality of storage slots, a buffer control operatively coupled to the buffer, a router operatively coupled to the buffer control and to a plurality of data sources, and a conflict detection unit operatively coupled to the router, to the buffer control, and to the plurality of data sources. The buffer temporarily stores information intended for storage in a memory bank. The buffer control determines a number of available storage slots in the buffer. The router routes data from the data sources to the buffer control. The conflict detection unit initiates a temporary halt of some of the data sources when the number of available storage slots is insufficient to store all of the data from data sources attempting to access the memory bank.

摘要翻译： turbo码解码器的存储器控​​制单元包括具有多个存储槽的缓冲器，可操作地耦合到缓冲器的缓冲器控制器，可操作地耦合到缓冲器控制和多个数据源的路由器，以及可操作地与冲突检测单元 耦合到路由器，到缓冲器控制和多个数据源。 缓冲器临时存储用于存储在存储体中的信息。 缓冲器控制确定缓冲器中可用的存储槽数。 路由器将数据源从数据源路由到缓冲区控制。 当可用存储时隙的数量不足以存储尝试访问存储体的数据源的所有数据时，冲突检测单元发起暂时停止某些数据源。

公开(公告)号：US20120219051A1

公开(公告)日：2012-08-30

申请号：US13405134

申请日：2012-02-24

申请人： Bei Yin ,  Kiarash Amiri ,  Joseph R. Cavallaro ,  Yuanbin Guo

发明人： Bei Yin ,  Kiarash Amiri ,  Joseph R. Cavallaro ,  Yuanbin Guo

IPC分类号： H03H7/30

CPC分类号： H04J11/004 ,  H04B1/71072 ,  H04L25/03159

摘要： A wireless receiver is constructed to equalize a time-domain received signal, detect a plurality of symbols of the equalized time-domain received signal, and perform interference cancellation on the time-domain received signal. The interference cancellation can be performed using a partial result produced by an IDFT, and may use only neighboring symbols in a detected plurality of symbols. The resulting wireless receiver can be constructed to operate efficiently under a plurality of wireless standards.

摘要翻译： 构造无线接收机以均衡时域接收信号，检测均衡的时域接收信号的多个符号，并对时域接收信号执行干扰消除。 可以使用IDFT产生的部分结果来执行干扰消除，并且可以仅使用检测到的多个符号中的相邻符号。 所得到的无线接收机可被构造成在多种无线标准下有效地工作。

公开(公告)号：US20120166742A1

公开(公告)日：2012-06-28

申请号：US13329065

申请日：2011-12-16

申请人： Guohui Wang ,  Yang Sun ,  Joseph R. Cavallaro ,  Yuanbin Guo

发明人： Guohui Wang ,  Yang Sun ,  Joseph R. Cavallaro ,  Yuanbin Guo

IPC分类号： G06F12/00

CPC分类号： H03M13/2957 ,  H03M13/395 ,  H03M13/3972 ,  H03M13/6561 ,  H03M13/6566

摘要： A memory control unit of a turbo code decoder includes a buffer having a plurality of storage slots, a buffer control operatively coupled to the buffer, a router operatively coupled to the buffer control and to a plurality of data sources, and a conflict detection unit operatively coupled to the router, to the buffer control, and to the plurality of data sources. The buffer temporarily stores information intended for storage in a memory bank. The buffer control determines a number of available storage slots in the buffer. The router routes data from the data sources to the buffer control. The conflict detection unit initiates a temporary halt of some of the data sources when the number of available storage slots is insufficient to store all of the data from data sources attempting to access the memory bank.

摘要翻译： turbo码解码器的存储器控​​制单元包括具有多个存储槽的缓冲器，可操作地耦合到缓冲器的缓冲器控制器，可操作地耦合到缓冲器控制和多个数据源的路由器，以及可操作地与冲突检测单元 耦合到路由器，到缓冲器控制和多个数据源。 缓冲器临时存储用于存储在存储体中的信息。 缓冲器控制确定缓冲器中可用的存储槽数。 路由器将数据源从数据源路由到缓冲区控制。 当可用存储时隙的数量不足以存储尝试访问存储体的数据源的所有数据时，冲突检测单元发起暂时停止某些数据源。

公开(公告)号：US20120240003A1

公开(公告)日：2012-09-20

申请号：US13479745

申请日：2012-05-24

申请人： Predrag Radosavljevic ,  Marjan Karkooti ,  Alexandre de Baynast ,  Joseph R. Cavallaro

发明人： Predrag Radosavljevic ,  Marjan Karkooti ,  Alexandre de Baynast ,  Joseph R. Cavallaro

IPC分类号： H03M13/11 ,  G06F11/10

CPC分类号： H03M13/1148 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/6566

摘要： The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Encoded data block comprising data sub-blocks are stored. Decoding is performed in a pipelined manner using an irregular, block-structured parity check matrix, where at least two data sub-block matrices of the parity check matrix are read from and written in each of a plurality of clock cycles. The reading and writing of the data sub-blocks is evenly distributed between at least two area of a memory. The decoding is performed with shift values which eliminate cycles at or below a predetermined threshold length. An apparatus, computer program product and device are also described.

摘要翻译： 本发明涉及低密度奇偶校验解码。 描述用于解码编码数据块的方法。 存储包括数据子块的编码数据块。 使用不规则的块结构的奇偶校验矩阵以流水线方式执行解码，其中奇偶校验矩阵的至少两个数据子块矩阵从多个时钟周期中的每一个读出并写入。 数据子块的读取和写入被均匀分布在存储器的至少两个区域之间。 以等于或低于预定阈值长度的周期的移位值执行解码。 还描述了一种装置，计算机程序产品和装置。

公开(公告)号：US08059761B2

公开(公告)日：2011-11-15

申请号：US12170474

申请日：2008-07-10

申请人： Kiarash Amiri ,  Christopher H. Dick ,  Raghavendar Mysore Rao ,  Joseph R. Cavallaro

发明人： Kiarash Amiri ,  Christopher H. Dick ,  Raghavendar Mysore Rao ,  Joseph R. Cavallaro

IPC分类号： H04L27/06

CPC分类号： H04L25/03229 ,  H04L25/0246 ,  H04L25/03968

摘要： Circuits detect communications from multiple transmitting antennas to multiple receiving antennas. A respective first block for each non-initial transmitting antenna determines partial distances for pairings of a first candidate and a quadrature-phase amplitude. A respective second block for the initial transmitting antenna determines partial distances for combinations of phase amplitudes. A respective second block for each non-initial transmitting antenna determines partial distances for pairings of a second candidate and an in-phase amplitude. A respective first selector for each non-initial transmitting antenna selects the first candidates from the pairings for the respective second block having smaller partial distances. A respective second selector for each non-initial transmitting antenna selects the second candidates from the pairings for the respective first block having smaller partial distances. An identifier circuit selects a final candidate with a smaller partial distance from the pairings of the respective second block for the last transmitting antenna.

摘要翻译： 电路检测从多个发射天线到多个接收天线的通信。 每个非初始发射天线的相应的第一块确定用于第一候选和正交相位振幅的配对的部分距离。 用于初始发射天线的相应的第二块确定相位振幅的组合的部分距离。 每个非初始发射天线的相应的第二块确定第二候选的配对和同相幅度的部分距离。 每个非初始发射天线的相应的第一选择器从具有较小部分距离的相应第二块的配对中选择第一候选。 每个非初始发射天线的相应的第二选择器从具有较小部分距离的相应第一块的配对中选择第二候选。 标识符电路从最后发射天线的相应第二块的配对中选择具有较小部分距离的最终候选。

公开(公告)号：US08219876B2

公开(公告)日：2012-07-10

申请号：US11977644

申请日：2007-10-24

申请人： Predrag Radosavljevic ,  Marjan Karkooti ,  Alexandre de Baynast ,  Joseph R. Cavallaro

发明人： Predrag Radosavljevic ,  Marjan Karkooti ,  Alexandre de Baynast ,  Joseph R. Cavallaro

IPC分类号： H03M13/00 ,  G11C29/00

CPC分类号： H03M13/1148 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/6566

摘要： The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Encoded data block comprising data sub-blocks are stored. Decoding is performed in a pipelined manner using an irregular, block-structured parity check matrix, where at least two data sub-block matrices of the parity check matrix are read from and written in each of a plurality of clock cycles. The reading and writing of the data sub-blocks is evenly distributed between at least two area of a memory. The decoding is performed with shift values which eliminate cycles at or below a predetermined threshold length. An apparatus, computer program product and device are also described.

摘要翻译： 本发明涉及低密度奇偶校验解码。 描述用于解码编码数据块的方法。 存储包括数据子块的编码数据块。 使用不规则的块结构的奇偶校验矩阵以流水线方式执行解码，其中奇偶校验矩阵的至少两个数据子块矩阵从多个时钟周期中的每一个读出并写入。 数据子块的读取和写入被均匀分布在存储器的至少两个区域之间。 以等于或低于预定阈值长度的周期的移位值执行解码。 还描述了一种装置，计算机程序产品和装置。

公开(公告)号：US20090232254A1

公开(公告)日：2009-09-17

申请号：US12045786

申请日：2008-03-11

申请人： Kiarash Amiri ,  Raghavendar Mysore Rao ,  Christopher H. Dick ,  Joseph R. Cavallaro

发明人： Kiarash Amiri ,  Raghavendar Mysore Rao ,  Christopher H. Dick ,  Joseph R. Cavallaro

IPC分类号： H04L27/00

CPC分类号： H04L25/03203 ,  H04L1/06 ,  H04L25/0208 ,  H04L25/0246 ,  H04L25/03184 ,  H04L25/03216 ,  H04L25/03292 ,  H04L2025/03426

摘要： A circuit detects symbols transmitted from multiple transmitting antennas to multiple receiving antennas. A distance block for an initial transmitting antenna in an ordering of the transmitting antennas determines a distance value for each symbol in a constellation. A selector block selects a limited number of candidates for the initial transmitting antenna from the symbols having smaller distance values. For each first and successive second transmitting antenna in the ordering, a distance-selector block selects a candidate for the second transmitting antenna for each candidate for the first transmitting antenna. The candidate for the second transmitting antenna is a pairing having a smaller distance value among the pairings of the candidate for the first transmitting antenna and the symbols. An identifier block selects a last candidate having a smaller distance value among the candidates for a last transmitting antenna in the ordering. The last candidate includes the detected symbols.

摘要翻译： 电路检测从多个发送天线发送到多个接收天线的符号。 在发射天线的排序中用于初始发射天线的距离块确定星座中每个符号的距离值。 选择器块从具有较小距离值的符号中选择用于初始发射天线的有限数量的候选。 对于排序中的每个第一和连续的第二发射天线，距离选择器块为第一发射天线的每个候选选择第二发射天线的候选。 第二发送天线的候选者是在第一发送天线和符号的候选对的配对中具有较小距离值的配对。 标识符块在排序中选择最后发射天线的候选中具有较小距离值的最后候选。 最后一个候选人包括检测到的符号。