公开(公告)号：US08621160B2

公开(公告)日：2013-12-31

申请号：US13329065

申请日：2011-12-16

申请人： Guohui Wang ,  Yang Sun ,  Joseph R. Cavallaro ,  Yuanbin Guo

发明人： Guohui Wang ,  Yang Sun ,  Joseph R. Cavallaro ,  Yuanbin Guo

IPC分类号： G06F12/06 ,  G06F13/376

CPC分类号： H03M13/2957 ,  H03M13/395 ,  H03M13/3972 ,  H03M13/6561 ,  H03M13/6566

摘要： A memory control unit of a turbo code decoder includes a buffer having a plurality of storage slots, a buffer control operatively coupled to the buffer, a router operatively coupled to the buffer control and to a plurality of data sources, and a conflict detection unit operatively coupled to the router, to the buffer control, and to the plurality of data sources. The buffer temporarily stores information intended for storage in a memory bank. The buffer control determines a number of available storage slots in the buffer. The router routes data from the data sources to the buffer control. The conflict detection unit initiates a temporary halt of some of the data sources when the number of available storage slots is insufficient to store all of the data from data sources attempting to access the memory bank.

摘要翻译： turbo码解码器的存储器控​​制单元包括具有多个存储槽的缓冲器，可操作地耦合到缓冲器的缓冲器控制器，可操作地耦合到缓冲器控制和多个数据源的路由器，以及可操作地与冲突检测单元 耦合到路由器，到缓冲器控制和多个数据源。 缓冲器临时存储用于存储在存储体中的信息。 缓冲器控制确定缓冲器中可用的存储槽数。 路由器将数据源从数据源路由到缓冲区控制。 当可用存储时隙的数量不足以存储尝试访问存储体的数据源的所有数据时，冲突检测单元发起暂时停止某些数据源。

公开(公告)号：US20120166742A1

公开(公告)日：2012-06-28

申请号：US13329065

申请日：2011-12-16

申请人： Guohui Wang ,  Yang Sun ,  Joseph R. Cavallaro ,  Yuanbin Guo

发明人： Guohui Wang ,  Yang Sun ,  Joseph R. Cavallaro ,  Yuanbin Guo

IPC分类号： G06F12/00

CPC分类号： H03M13/2957 ,  H03M13/395 ,  H03M13/3972 ,  H03M13/6561 ,  H03M13/6566

摘要： A memory control unit of a turbo code decoder includes a buffer having a plurality of storage slots, a buffer control operatively coupled to the buffer, a router operatively coupled to the buffer control and to a plurality of data sources, and a conflict detection unit operatively coupled to the router, to the buffer control, and to the plurality of data sources. The buffer temporarily stores information intended for storage in a memory bank. The buffer control determines a number of available storage slots in the buffer. The router routes data from the data sources to the buffer control. The conflict detection unit initiates a temporary halt of some of the data sources when the number of available storage slots is insufficient to store all of the data from data sources attempting to access the memory bank.

摘要翻译： turbo码解码器的存储器控​​制单元包括具有多个存储槽的缓冲器，可操作地耦合到缓冲器的缓冲器控制器，可操作地耦合到缓冲器控制和多个数据源的路由器，以及可操作地与冲突检测单元 耦合到路由器，到缓冲器控制和多个数据源。 缓冲器临时存储用于存储在存储体中的信息。 缓冲器控制确定缓冲器中可用的存储槽数。 路由器将数据源从数据源路由到缓冲区控制。 当可用存储时隙的数量不足以存储尝试访问存储体的数据源的所有数据时，冲突检测单元发起暂时停止某些数据源。

公开(公告)号：US08767849B2

公开(公告)日：2014-07-01

申请号：US13405134

申请日：2012-02-24

申请人： Bei Yin ,  Kiarash Amiri ,  Joseph R. Cavallaro ,  Yuanbin Guo

发明人： Bei Yin ,  Kiarash Amiri ,  Joseph R. Cavallaro ,  Yuanbin Guo

IPC分类号： H04K1/10 ,  H04L27/28 ,  H04L25/03 ,  H04J11/00 ,  H04B1/7107

CPC分类号： H04J11/004 ,  H04B1/71072 ,  H04L25/03159

摘要： A wireless receiver is constructed to equalize a time-domain received signal, detect a plurality of symbols of the equalized time-domain received signal, and perform interference cancellation on the time-domain received signal. The interference cancellation can be performed using a partial result produced by an IDFT, and may use only neighboring symbols in a detected plurality of symbols. The resulting wireless receiver can be constructed to operate efficiently under a plurality of wireless standards.

摘要翻译： 构造无线接收机以均衡时域接收信号，检测均衡的时域接收信号的多个符号，并对时域接收信号执行干扰消除。 可以使用由IDFT产生的部分结果来执行干扰消除，并且可以仅使用检测到的多个符号中的相邻符号。 所得到的无线接收机可被构造成在多种无线标准下有效地工作。

公开(公告)号：US07492815B2

公开(公告)日：2009-02-17

申请号：US10997397

申请日：2004-11-24

申请人： Yuanbin Guo ,  Jianzhong Zhang ,  Dennis McCain ,  Joseph R. Cavallaro

发明人： Yuanbin Guo ,  Jianzhong Zhang ,  Dennis McCain ,  Joseph R. Cavallaro

IPC分类号： H04B1/707 ,  H03H7/30

CPC分类号： H04L25/03038 ,  H04B1/71055 ,  H04L25/0204 ,  H04L25/021 ,  H04L25/0242 ,  H04L25/0328 ,  H04L2025/03375 ,  H04L2025/03426 ,  H04L2025/03477 ,  H04L2025/03605

摘要： Disclosed is a LMMSE receiver that restores orthogonality of spreading codes in the downlink channel for a spread spectrum signal received over N receive antennas. The FFT-based chip equalizer tap solver reduces the direct matrix inverse of the prior art to the inverse of some submatrices of size N×N with the dimension of the receive antennas, and most efficiently reduces matrix inverses to no larger than 2×2. Complexity is further reduced over a conventional Fast Fourier Transform approach by Hermitian optimization to the inverse of submatrices and tree pruning. For a receiver with N=4 or N=2 with double oversampling, the resulting 4×4 matrices are partitioned into 2×2 block sub-matrices, inverted, and rebuilt into a 4×4 matrix. Common computations are found and repeated computations are eliminated to improve efficiency. Generic design architecture is derived from the special design blocks to eliminate redundancies in complex operations. Optimally, the architecture is parallel and pipelined.

摘要翻译： 公开了一种用于在N个接收天线上接收的扩频信号的下行链路信道中恢复扩频码的正交性的LMMSE接收机。 基于FFT的码片均衡器抽头解算器将现有技术的直接矩阵逆减少为具有接收天线的尺寸的尺寸为N×N的一些子矩阵的倒数，并且最有效地将矩阵反转减小到不大于2×2。 通过Hermitian优化，传统的快速傅立叶变换方法，复杂度进一步降低到子矩阵和树剪枝的倒数。 对于具有N = 4或N = 2的具有双重过采样的接收机，所得到的4×4矩阵被划分为2x2块子矩阵，被反转并重建为4×4矩阵。 发现常规计算，消除重复计算以提高效率。 通用设计架构源于特殊的设计模块，以消除复杂操作中的冗余。 最佳的架构是并行和流水线的。

公开(公告)号：US07706430B2

公开(公告)日：2010-04-27

申请号：US11067498

申请日：2005-02-25

申请人： Yuanbin Guo ,  Dennis McCain ,  Joseph R. Cavallaro

发明人： Yuanbin Guo ,  Dennis McCain ,  Joseph R. Cavallaro

IPC分类号： H04L27/06

CPC分类号： H04B1/71075 ,  H04B2001/71077 ,  H04B2201/70707

摘要： A system, apparatus and method for a multi-stage Parallel Residue Compensation (PRC) receiver for enhanced suppression of the Multiple Access Interference (MAI) in Code Division Multiple Access (CDMA) systems. The accuracy of the interference estimation is improved with a set of weights computed from an adaptive Normalized Least Mean Square (NLMS) algorithm. In order to reduce complexity, the commonality of the multi-code processing is extracted and used to derive a structure of PRC to avoid direct interference cancellation. The derived PRC structure reduces the interference cancellation architecture from a complexity that is proportional to the square of the number of users to a complexity that is linear with respect to the number of users. The complexity is further reduced by replacing dedicated multiplier circuits with simple combinational logic.

摘要翻译： 一种用于增强抑制码分多址（CDMA）系统中的多址干扰（MAI）的多级并行残差补偿（PRC）接收机的系统，装置和方法。 通过从自适应归一化最小二乘法（NLMS）算法计算的一组权重，改善了干扰估计的准确性。 为了降低复杂度，提取多码处理的通用性，并用于导出PRC的结构，以避免直接干扰消除。 导出的PRC结构从与用户数量的平方成正比于与用户数量相关的复杂度的复杂度降低了干扰消除架构。 通过用简单的组合逻辑替换专用乘法电路，进一步降低了复杂度。

公开(公告)号：US20120219051A1

公开(公告)日：2012-08-30

申请号：US13405134

申请日：2012-02-24

申请人： Bei Yin ,  Kiarash Amiri ,  Joseph R. Cavallaro ,  Yuanbin Guo

发明人： Bei Yin ,  Kiarash Amiri ,  Joseph R. Cavallaro ,  Yuanbin Guo

IPC分类号： H03H7/30

CPC分类号： H04J11/004 ,  H04B1/71072 ,  H04L25/03159

摘要： A wireless receiver is constructed to equalize a time-domain received signal, detect a plurality of symbols of the equalized time-domain received signal, and perform interference cancellation on the time-domain received signal. The interference cancellation can be performed using a partial result produced by an IDFT, and may use only neighboring symbols in a detected plurality of symbols. The resulting wireless receiver can be constructed to operate efficiently under a plurality of wireless standards.

摘要翻译： 构造无线接收机以均衡时域接收信号，检测均衡的时域接收信号的多个符号，并对时域接收信号执行干扰消除。 可以使用IDFT产生的部分结果来执行干扰消除，并且可以仅使用检测到的多个符号中的相邻符号。 所得到的无线接收机可被构造成在多种无线标准下有效地工作。

公开(公告)号：US08559540B2

公开(公告)日：2013-10-15

申请号：US12904622

申请日：2010-10-14

申请人： Yang Sun ,  Joseph R. Cavallaro ,  Jorma Lilleberg

发明人： Yang Sun ,  Joseph R. Cavallaro ,  Jorma Lilleberg

IPC分类号： H04L5/12 ,  H04L27/06 ,  H03M13/03

CPC分类号： H03M13/6525 ,  H03M13/1102 ,  H03M13/3905 ,  H04L1/06 ,  H04L25/03216 ,  H04L25/03891

摘要： An apparatus for trellis-based detection in a communication system including a processor and memory having computer program code configured to construct a trellis representing a transmitted signal formed from a plurality of symbols, each having a constellation size, transmitted by a number of transmit antennas, and form a log likelihood ratio at nodes of the trellis as a log-sum of a number of exponential terms corresponding to a hypothesized transmitted bit value of the plurality of symbols. The number of exponential terms is limited by a number of most likely paths of the trellis extending from each node of the trellis and the constellation size. The processor and memory including computer program code are further configured to form a list at each node of the trellis of a size limited to the number of the most likely paths of the trellis extending from each node of the trellis.

摘要翻译： 一种用于包括处理器和存储器的通信系统中的基于网格检测的装置，所述计算机程序代码被配置为构造表示从多个符号形成的发送信号的网格，所述多个符号具有由多个发送天线发送的星座大小， 并且在网格的节点处形成对数似然比，作为对应于多个符号的假设的发送比特值的指数项的数量的对数和。 指数项的数量受到从网格的每个节点和星座大小延伸的网格的最可能路径的数量的限制。 包括计算机程序代码的处理器和存储器还被配置为在格架的每个节点处形成列表，其大小限于从网格的每个节点延伸的网格的最可能路径的数量。

公开(公告)号：US08477862B2

公开(公告)日：2013-07-02

申请号：US12959007

申请日：2010-12-02

申请人： Yang Sun ,  Joseph R. Cavallaro ,  Jorma Lilleberg

发明人： Yang Sun ,  Joseph R. Cavallaro ,  Jorma Lilleberg

IPC分类号： H04L5/12

CPC分类号： H04L25/03216 ,  H04B7/0413 ,  H04L1/005 ,  H04L1/0055 ,  H04L25/03171 ,  H04L2025/03426

摘要： An apparatus for trellis-based detection in a communication system including a processor and memory having computer program code configured to construct a trellis representing a transmitted signal formed from a plurality of symbols, each having a constellation size, transmitted by a number of transmit antennas, and form a log likelihood ratio at nodes of the trellis as a log-sum of a number of exponential terms including a priori information corresponding to a hypothesized transmitted bit value of the plurality of symbols. The number of exponential terms is limited by a number of most likely paths of the trellis extending from each node of the trellis and the constellation size. The processor and memory including computer program code are configured to form a list at each node of the trellis of a size limited to the number of the most likely paths of the trellis extending from each node.

摘要翻译： 一种用于包括处理器和存储器的通信系统中的基于网格检测的装置，所述计算机程序代码被配置为构造表示从多个符号形成的发送信号的网格，所述多个符号具有由多个发送天线发送的星座大小， 并且在网格的节点处形成对数似然比，作为包括与多个符号的假定的发送比特值相对应的先验信息的指数项的数量的对数和。 指数项的数量受到从网格的每个节点和星座大小延伸的网格的最可能路径的数量的限制。 包括计算机程序代码的处理器和存储器被配置为在格局的每个节点处形成列表，其大小限于从每个节点延伸的网格的最可能路径的数量。

公开(公告)号：US20120093249A1

公开(公告)日：2012-04-19

申请号：US12959007

申请日：2010-12-02

申请人： Yang Sun ,  Joseph R. Cavallaro ,  Jorma Lilleberg

发明人： Yang Sun ,  Joseph R. Cavallaro ,  Jorma Lilleberg

IPC分类号： H04L23/02

CPC分类号： H04L25/03216 ,  H04B7/0413 ,  H04L1/005 ,  H04L1/0055 ,  H04L25/03171 ,  H04L2025/03426

摘要： An apparatus for trellis-based detection in a communication system including a processor and memory having computer program code configured to construct a trellis representing a transmitted signal formed from a plurality of symbols, each having a constellation size, transmitted by a number of transmit antennas, and form a log likelihood ratio at nodes of the trellis as a log-sum of a number of exponential terms including a priori information corresponding to a hypothesized transmitted bit value of the plurality of symbols. The number of exponential terms is limited by a number of most likely paths of the trellis extending from each node of the trellis and the constellation size. The processor and memory including computer program code are configured to form a list at each node of the trellis of a size limited to the number of the most likely paths of the trellis extending from each node.

摘要翻译： 一种用于包括处理器和存储器的通信系统中的基于网格检测的装置，所述计算机程序代码被配置为构造表示从多个符号形成的发送信号的网格，所述多个符号具有由多个发送天线发送的星座大小， 并且在网格的节点处形成对数似然比，作为包括与多个符号的假定的发送比特值相对应的先验信息的指数项的数量的对数和。 指数项的数量受到从网格的每个节点和星座大小延伸的网格的最可能路径的数量的限制。 包括计算机程序代码的处理器和存储器被配置为在格局的每个节点处形成列表，其大小限于从每个节点延伸的网格的最可能路径的数量。

公开(公告)号：US20100303176A1

公开(公告)日：2010-12-02

申请号：US12475755

申请日：2009-06-01

申请人： Jorma Olavi Lilleberg ,  Yang Sun ,  Joseph R. Cavallaro

发明人： Jorma Olavi Lilleberg ,  Yang Sun ,  Joseph R. Cavallaro

IPC分类号： H04L27/06

CPC分类号： H04L25/03203 ,  H04L25/03318 ,  H04L2025/03426

摘要： Methods and apparatuses are provided for MIMO detection. A method may include considering a symbol vector received over MIMO system. The method may further include generating a list comprising a predefined number of candidate transmit symbol vectors based at least in part upon the received symbol vector using a trellis comprising a plurality of nodes that apply distributed list decoding to generate the list, wherein the list of the predefined number of candidate transmit symbol vectors comprises the predefined number of candidate transmit symbol vectors derived from the set of all possible trellis paths as determined based at least in part upon the respective cumulative trellis path weights. Corresponding apparatuses are also provided.

摘要翻译： 提供了用于MIMO检测的方法和装置。 一种方法可以包括考虑通过MIMO系统接收的符号向量。 该方法可以进一步包括至少部分地基于所接收的符号向量来生成包括预定数量的候选发射符号向量的列表，所述符号向量使用包括多个节点的网格，所述节点应用分布式列表解码以生成所述列表，其中， 预定数量的候选发送符号向量包括从至少部分地基于相应的累积网格路径权重确定的所有可能网格路径的集合导出的预定数量的候选发射符号向量。 还提供了相应的装置。