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130 条记录 (耗时 0.051 秒)

    Image display device and driving method thereof
    1.
    发明授权
    Image display device and driving method thereof 有权
    图像显示装置及其驱动方法

    公开(公告)号：US07663613B2

    公开(公告)日：2010-02-16

    申请号：US10159288

    申请日：2002-06-03

    申请人： Yukio Tanaka ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

    发明人： Yukio Tanaka ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

    IPC分类号： G09G5/00 ,  G06F3/038

    CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0297

    摘要： An occupying area of a digital system signal line driver circuit in an image display device is large and this hinders the miniaturization of the display device. A memory circuit and a D/A converter circuit in the signal line driver circuit are commonly used for n (“n” is a natural number equal to or larger than 2) signal lines. One horizontal scanning period is divided into n periods and the memory circuit and the D/A converter circuit each perform processing for different signal lines during each of the divided periods. Thus, all the signal lines can be driven. Therefore, the number of memory circuits and the number of D/A converter circuits in the signal line driver circuit can be reduced to one n-th in a conventional case.

    摘要翻译： 图像显示装置中的数字系统信号线驱动电路的占有面积大，妨碍显示装置的小型化。 信号线驱动电路中的存储电路和D / A转换电路通常用于n（“n”是等于或大于2的自然数）的信号线。 一个水平扫描周期被分为n个周期，并且存储器电路和D / A转换器电路在每个分割周期期间各自执行不同信号线的处理。 因此，可以驱动所有的信号线。 因此，在常规情况下，信号线驱动电路中的存储电路数量和D / A转换电路的数量可以减少到1 / n。

    Image display device and driving method thereof
    2.
    发明授权
    Image display device and driving method thereof 失效
    图像显示装置及其驱动方法

    公开(公告)号：US08325170B2

    公开(公告)日：2012-12-04

    申请号：US12639049

    申请日：2009-12-16

    申请人： Yukio Tanaka ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

    发明人： Yukio Tanaka ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

    IPC分类号： G09G5/00 ,  G06F3/038

    CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0297

    摘要： An occupying area of a digital system signal line driver circuit in an image display device is large and this hinders the miniaturization of the display device. A memory circuit and a D/A converter circuit in the signal line driver circuit are commonly used for n (“n” is a natural number equal to or larger than 2) signal lines. One horizontal scanning period is divided into n periods and the memory circuit and the D/A converter circuit each perform processing for different signal lines during each of the divided periods. Thus, all the signal lines can be driven. Therefore, the number of memory circuits and the number of D/A converter circuits in the signal line driver circuit can be reduced to one n-th in a conventional case.

    摘要翻译： 图像显示装置中的数字系统信号线驱动电路的占有面积大，妨碍显示装置的小型化。 信号线驱动电路中的存储电路和D / A转换电路通常用于n（n为等于或大于2的自然数）信号线。 一个水平扫描周期被分为n个周期，并且存储器电路和D / A转换器电路在每个分割周期期间各自执行不同信号线的处理。 因此，可以驱动所有的信号线。 因此，在常规情况下，信号线驱动电路中的存储电路数量和D / A转换电路的数量可以减少到1 / n。

    Image Display Device and Driving Method Thereof
    3.
    发明申请
    Image Display Device and Driving Method Thereof 失效
    图像显示装置及其驱动方法

    公开(公告)号：US20100090994A1

    公开(公告)日：2010-04-15

    申请号：US12639049

    申请日：2009-12-16

    申请人： Yukio Tanaka ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

    发明人： Yukio Tanaka ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

    IPC分类号： G09G5/00 ,  G09G3/36 ,  H04N5/66

    CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0297

    摘要： An occupying area of a digital system signal line driver circuit in an image display device is large and this hinders the miniaturization of the display device. A memory circuit and a D/A converter circuit in the signal line driver circuit are commonly used for n (“n” is a natural number equal to or larger than 2) signal lines. One horizontal scanning period is divided into n periods and the memory circuit and the D/A converter circuit each perform processing for different signal lines during each of the divided periods. Thus, all the signal lines can be driven. Therefore, the number of memory circuits and the number of D/A converter circuits in the signal line driver circuit can be reduced to one n-th in a conventional case.

    摘要翻译： 图像显示装置中的数字系统信号线驱动电路的占有面积大，妨碍显示装置的小型化。 信号线驱动电路中的存储电路和D / A转换电路通常用于n（“n”是等于或大于2的自然数）的信号线。 一个水平扫描周期被分为n个周期，并且存储器电路和D / A转换器电路在每个分割周期期间各自执行不同信号线的处理。 因此，可以驱动所有的信号线。 因此，在常规情况下，信号线驱动电路中的存储电路数量和D / A转换电路的数量可以减少到1 / n。

    Image display device, method of driving thereof, and electronic equipment
    4.
    发明授权
    Image display device, method of driving thereof, and electronic equipment 有权
    图像显示装置，其驱动方法和电子设备

    公开(公告)号：US06693616B2

    公开(公告)日：2004-02-17

    申请号：US09782260

    申请日：2001-02-14

    申请人： Jun Koyama ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

    发明人： Jun Koyama ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

    IPC分类号： G09G336

    CPC分类号： G09G3/3688 ,  G09G2310/0259 ,  G09G2310/027 ,  G09G2310/0297

    摘要： The surface area occupied by a digital type signal line driver circuit in an image display device is large, and this is an impediment to reducing the size of the display device. A memory circuit within a signal line driver circuit is made common among n signal lines (where n is a natural number greater than or equal to 2). One horizontal scan period is divided into n divisions, and all signal lines can be driven by performing processing with respect to signal lines differing by memory circuit and D/A converter circuit, respectively, during the period of each division. It thus becomes possible to make 1/n as many memory circuits and D/A conversion circuits within the signal line driver circuit as in a conventional example.

    摘要翻译： 图像显示装置中的数字式信号线驱动电路所占据的表面积较大，这是减小显示装置尺寸的障碍。 信号线驱动电路内的存储电路在n条信号线（其中n为大于或等于2的自然数）之间是共同的。 一个水平扫描周期被划分为n个分区，并且在每个划分期间分别通过对与存储电路和D / A转换器电路不同的信号线执行处理来驱动所有的信号线。 因此，与现有例一样，能够使信号线驱动电路内的1 / n的存储电路和D / A转换电路成为可能。

    Signal processing circuit, low-voltage signal generator and image display incorporating the same
    5.
    发明授权
    Signal processing circuit, low-voltage signal generator and image display incorporating the same 有权
    信号处理电路，低压信号发生器和包含其的图像显示

    公开(公告)号：US07978169B2

    公开(公告)日：2011-07-12

    申请号：US12071529

    申请日：2008-02-21

    申请人： Hidehiko Yamashita ,  Hajime Washio ,  Yasushi Kubota ,  Graham Andrew Cairns ,  Michael James Brownlow

    发明人： Hidehiko Yamashita ,  Hajime Washio ,  Yasushi Kubota ,  Graham Andrew Cairns ,  Michael James Brownlow

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3688 ,  G09G3/20 ,  G09G2310/0289 ,  G09G2330/021

    摘要： There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.

    摘要翻译： 提供：第一逻辑运算电路，其使用高幅度逻辑信号执行逻辑运算; 具有负载电容的传输系统; 以及作为降压电平移位器的低压信号发生器，其将来自第一逻辑运算电路的输入高幅度逻辑信号变换为具有比高幅度逻辑信号更低的振幅的低幅度逻辑信号，以输出到 传输系统。 在该结构中，第一逻辑运算电路基于高幅度逻辑信号进行动作，因此没有故障，高速运转。 此外，引入负载电容的传输系统发送低幅度逻辑信号，因此抑制电力消耗的增加和不必要的辐射的发生。

    Shift register and image display apparatus using the same
    9.
    发明授权
    Shift register and image display apparatus using the same 有权
    移位寄存器和使用其的图像显示装置

    公开(公告)号：US06909417B2

    公开(公告)日：2005-06-21

    申请号：US09578440

    申请日：2000-05-25

    申请人： Hajime Washio ,  Yasushi Kubota ,  Kazuhiro Maeda ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

    发明人： Hajime Washio ,  Yasushi Kubota ,  Kazuhiro Maeda ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

    IPC分类号： G11C19/00 ,  G09G3/20 ,  G09G3/36

    CPC分类号： G09G3/3688 ,  G09G2300/0408 ,  G09G2310/0289 ,  G09G2330/021

    摘要： A level shifter 13 is provided for each of SR flip flops F1 constituting a shift register 11. The level shifter 13 increases a voltage of a clock signal CK. This arrangement reduces a distance for transmitting a clock signal whose voltage has been increased, as compared with a construction in which a voltage of a clock signal is increased by a single level shifter and the signal is transmitted to each of the flip flops; consequently, a load capacity of the level shifter can be smaller. Furthermore, each of the level shifters is operated during a pulse output of the previous level shifter 13, and the operation is suspended at the end of the pulse output. Thus, the level shifters 13 can operate only when it is necessary to apply a clock signal CK to the corresponding SR flip flop F1. As a result, even when an amplitude of a clock signal is small, it is possible to reduce power consumption of the shift resister under normal operation.

    摘要翻译： 为构成移位寄存器11的每个SR触发器F 1提供电平移位器13.电平移位器13增加时钟信号CK的电压。 与通过单个电平移位器增加时钟信号的电压并且将信号发送到每个触发器的结构相比，这种布置减少了用于传输电压已经增加的时钟信号的距离; 因此，电平转换器的负载能力可以更小。 此外，每个电平移位器在先前电平移位器13的脉冲输出期间操作，并且在脉冲输出结束时暂停操作。 因此，只有当需要对相应的SR触发器F 1施加时钟信号CK时，电平移位器13才能够工作。结果，即使当时钟信号的幅度小时，也可以降低功耗 的正常运行中的移位寄存器。

    Shift register circuit, image display apparatus having the circuit, and driving method for LCD devices
    10.
    发明授权
    Shift register circuit, image display apparatus having the circuit, and driving method for LCD devices 有权
    移位寄存器电路，具有电路的图像显示装置以及LCD装置的驱动方法

    公开(公告)号：US06879313B1

    公开(公告)日：2005-04-12

    申请号：US09523511

    申请日：2000-03-10

    申请人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida ,  Kazuhiro Maeda ,  Hiroshi Yoneda

    发明人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida ,  Kazuhiro Maeda ,  Hiroshi Yoneda

    IPC分类号： G09G3/36 ,  G11C19/28 ,  G11C19/00

    CPC分类号： G09G3/3688 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0233 ,  G11C19/28

    摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

    摘要翻译： 移位寄存器电路包括串联连接的多个锁存电路，以顺序地将脉冲信号ST从一个传送到另一个，一个发送时钟信号CLK的时钟信号线以及执行时钟信号之间的电连接和断开的多个开关电路 线和多个锁存电路。 在接通移位寄存器时，至少一个开关电路将至少一个锁存电路与时钟信号线电断开。 在电源接通之后的初始化期间，时钟信号CLK的频率比正常运行期间低，并且在正常运行期间逐渐增大。