公开(公告)号：US06879313B1

公开(公告)日：2005-04-12

申请号：US09523511

申请日：2000-03-10

申请人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida ,  Kazuhiro Maeda ,  Hiroshi Yoneda

发明人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida ,  Kazuhiro Maeda ,  Hiroshi Yoneda

IPC分类号： G09G3/36 ,  G11C19/28 ,  G11C19/00

CPC分类号： G09G3/3688 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0233 ,  G11C19/28

摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

摘要翻译： 移位寄存器电路包括串联连接的多个锁存电路，以顺序地将脉冲信号ST从一个传送到另一个，一个发送时钟信号CLK的时钟信号线以及执行时钟信号之间的电连接和断开的多个开关电路 线和多个锁存电路。 在接通移位寄存器时，至少一个开关电路将至少一个锁存电路与时钟信号线电断开。 在电源接通之后的初始化期间，时钟信号CLK的频率比正常运行期间低，并且在正常运行期间逐渐增大。

公开(公告)号：US07173598B2

公开(公告)日：2007-02-06

申请号：US11063718

申请日：2005-02-22

申请人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida ,  Kazuhiro Maeda ,  Hiroshi Yoneda

发明人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida ,  Kazuhiro Maeda ,  Hiroshi Yoneda

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0233 ,  G11C19/28

摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

公开(公告)号：US20050168252A1

公开(公告)日：2005-08-04

申请号：US11063718

申请日：2005-02-23

申请人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida ,  Kazuhiro Maeda ,  Hiroshi Yoneda

发明人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida ,  Kazuhiro Maeda ,  Hiroshi Yoneda

IPC分类号： G09G3/36 ,  G11C19/28 ,  H03L7/00

CPC分类号： G09G3/3688 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0233 ,  G11C19/28

摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

公开(公告)号：US20050140621A1

公开(公告)日：2005-06-30

申请号：US11060963

申请日：2005-02-18

申请人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida

发明人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida

IPC分类号： G09G3/36 ,  G11C19/28

CPC分类号： G09G3/3688 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0233 ,  G11C19/28

摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

公开(公告)号：US07375708B2

公开(公告)日：2008-05-20

申请号：US10105652

申请日：2002-03-25

申请人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida ,  Yasuhiro Yoshida ,  Hiroyuki Furukawa

发明人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida ,  Yasuhiro Yoshida ,  Hiroyuki Furukawa

IPC分类号： G09G3/36

CPC分类号： G09G3/2011 ,  G09G3/2051 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2310/027 ,  G09G2310/0297

摘要： A data signal line drive circuit supplying a video signal to a pixel array performs pseudo tone gradation processing with respect to the video signal that is sent to an n number of data signal lines SL by m (

摘要翻译： 向像素阵列提供视频信号的数据信号线驱动电路相对于通过伪色调灰度处理的m（

公开(公告)号：US07193604B2

公开(公告)日：2007-03-20

申请号：US11060963

申请日：2005-02-18

申请人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida

发明人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0233 ,  G11C19/28

摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

摘要翻译： 移位寄存器电路包括串联连接的多个锁存电路，以顺序地将脉冲信号ST从一个传送到另一个，一个发送时钟信号CLK的时钟信号线以及执行时钟信号之间的电连接和断开的多个开关电路 线和多个锁存电路。 在接通移位寄存器时，至少一个开关电路将至少一个锁存电路与时钟信号线电断开。 在电源接通之后的初始化期间，时钟信号CLK的频率比正常运行期间低，并且在正常运行期间逐渐增大。

公开(公告)号：US06873313B2

公开(公告)日：2005-03-29

申请号：US09822768

申请日：2001-03-30

申请人： Hajime Washio ,  Nobuhiro Kuwabara ,  Hiroshi Yoneda ,  Shigeto Yoshida

发明人： Hajime Washio ,  Nobuhiro Kuwabara ,  Hiroshi Yoneda ,  Shigeto Yoshida

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/3614 ,  G09G3/3685 ,  G09G2310/0232 ,  G09G2310/0251 ,  G09G2330/021

摘要： An image display device of this invention includes a pre-charging voltage stabilizing section having current controlling means and charge holding means which respectively include a resistor and a capacitor to stabilize a pre-charging voltage. The charge holding means holds a voltage to be supplied to data signal lines, and the current controlling means suppresses a current flow from a control signal generating circuit, thereby suppressing power fluctuation at the control signal generating circuit. This suppresses fluctuation in the pre-charging voltage and enables data signal lines to be charged to a predetermined voltage, thereby suppressing deterioration of image quality and an increase in power consumption of the image display device. Further, when using the pre-charging voltage stabilizing section and setting a portion of a display as a video data non-display area avoiding display of video data in a non-match image display mode to display at fixed brightness in the video data non-display area by a pre-charging voltage from a pre-charging circuit, a control signal is suspended in a fixed period, thus realizing a non-match image display mode to display a video image of an aspect ratio different from that of a screen of a display without impairing an image quality, and saving power.

摘要翻译： 本发明的图像显示装置包括具有电流控制装置和电荷保持装置的预充电电压稳定部分，其分别包括用于稳定预充电电压的电阻器和电容器。 电荷保持装置保持要提供给数据信号线的电压，并且电流控制装置抑制来自控制信号发生电路的电流，从而抑制控制信号发生电路的功率波动。 这抑制了预充电电压的波动，并且能够使数据信号线被充电到预定电压，从而抑制图像质量的劣化和图像显示装置的功耗的增加。 此外，当使用预充电电压稳定部分并且将显示器的一部分设置为视频数据非显示区域时，避免以不匹配的图像显示模式显示视频数据，以在视频数据非显示区域中以固定亮度显示， 通过来自预充电电路的预充电电压来显示区域，控制信号以固定的时间段被暂停，从而实现不匹配的图像显示模式，以显示不同于屏幕的宽高比的视频图像 显示而不损害图像质量，并且节省电力。

公开(公告)号：US07042431B1

公开(公告)日：2006-05-09

申请号：US09711009

申请日：2000-11-09

申请人： Hajime Washio ,  Nobuhiro Kuwabara ,  Shigeto Yoshida ,  Yuji Asoh ,  Hiroshi Yoneda

发明人： Hajime Washio ,  Nobuhiro Kuwabara ,  Shigeto Yoshida ,  Yuji Asoh ,  Hiroshi Yoneda

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G2310/0251 ,  G09G2320/0233

摘要： In a vertical retrace interval, a pre-charge potential or a signal potential is applied to each polarity for AC driving liquid crystal at least once each, so as to maintain fluctuations in pixel potential between the positive polarity side and the negative polarity side uniform, and minimum required potentials are supplied to the data signal line, thereby suppressing decrease in image quality without significantly increasing power consumption.

摘要翻译： 在垂直回扫间隔中，对交流驱动液晶的各极性施加预充电电位或信号电位至少一次，以保持正极侧和负极侧之间的像素电位的波动均匀， 并且将最小所需电位提供给数据信号线，从而在不显着增加功耗的情况下抑制图像质量的降低。

公开(公告)号：US07339570B2

公开(公告)日：2008-03-04

申请号：US09851885

申请日：2001-05-09

申请人： Yasushi Kubota ,  Hajime Washio ,  Michael James Brownlow ,  Graham Andrew Cairns ,  Yasuyoshi Kaise ,  Kazuhiro Maeda

发明人： Yasushi Kubota ,  Hajime Washio ,  Michael James Brownlow ,  Graham Andrew Cairns ,  Yasuyoshi Kaise ,  Kazuhiro Maeda

IPC分类号： G09G3/36

CPC分类号： G09G3/2011 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G5/005 ,  G09G5/006 ,  G09G2300/0456 ,  G09G2310/0205 ,  G09G2310/0248 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2320/0626 ,  G09G2330/021 ,  G09G2340/0428 ,  G09G2340/10 ,  G09G2340/12 ,  G09G2360/144 ,  H01L27/124 ,  H04N2007/145

摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.

摘要翻译： 图像显示装置包括两个数据信号线驱动电路和彼此不同地配置的两个扫描信号线驱动电路。 不同的数据信号线驱动电路和扫描信号线驱动电路兼容不同的显示格式。 可以以最合适的显示格式生产显示器，并且可以通过根据输入视频的类型和环境条件的开关操作驱动电路来降低功耗。 此外，通过使用多个驱动电路将视频信号以时间滞后的方式写入信号线，可以在另一图像上写入图像; 因此，可以在不外部处理视频信号的情况下产生叠加显示。 因此，可以在图像显示装置中实现令人满意的图像显示和低功耗。

公开(公告)号：US20050243588A1

公开(公告)日：2005-11-03

申请号：US11091012

申请日：2005-03-25

申请人： Yasushi Kubota ,  Hajime Washio ,  Michael Brownlow ,  Graham Cairns ,  Yasuyoshi Kaise ,  Kazuhiro Maeda

发明人： Yasushi Kubota ,  Hajime Washio ,  Michael Brownlow ,  Graham Cairns ,  Yasuyoshi Kaise ,  Kazuhiro Maeda

IPC分类号： G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  H01L21/77 ,  H01L21/84 ,  G11C5/06

CPC分类号： G09G3/2011 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G5/005 ,  G09G5/006 ,  G09G2300/0456 ,  G09G2310/0205 ,  G09G2310/0248 ,  G09G2310/027 ,  G09G2310/0281 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2320/0626 ,  G09G2330/021 ,  G09G2340/0428 ,  G09G2340/10 ,  G09G2340/12 ,  G09G2360/144 ,  H01L27/124 ,  H04N2007/145

摘要： An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.

摘要翻译： 图像显示装置包括两个数据信号线驱动电路和彼此不同地配置的两个扫描信号线驱动电路。 不同的数据信号线驱动电路和扫描信号线驱动电路兼容不同的显示格式。 可以以最合适的显示格式生产显示器，并且可以通过根据输入视频的类型和环境条件的开关操作驱动电路来降低功耗。 此外，通过使用多个驱动电路将视频信号以时间滞后的方式写入信号线，可以在另一图像上写入图像; 因此，可以在不外部处理视频信号的情况下产生叠加显示。 因此，可以在图像显示装置中实现令人满意的图像显示和低功耗。