公开(公告)号：US06442622B1

公开(公告)日：2002-08-27

申请号：US09419054

申请日：1999-10-15

申请人： Yusuke Yamamoto ,  Ritsuo Matsushita ,  Yasuyuki Muraki

发明人： Yusuke Yamamoto ,  Ritsuo Matsushita ,  Yasuyuki Muraki

IPC分类号： G06F1300

CPC分类号： G06F9/345

摘要： A digital signal processor and digital signal processing method are provided, which are capable of performing plural kinds of signal processing, and also performing processing for storing sampled data in a manner corresponding to respective kinds of signal processing with a small amount of hardware even in the case where the manner of storing and reading sampled data to be processed with respect to a memory device is different between the plural kinds of signal processing. A storage device stores plural kinds of sampled data corresponding, respectively, to plural kinds of signal processing. A counter updates a count value thereof every sampling period and generates the updated count value as a basic address. A sampled data input and output device performs an input and output operation every sampling period, the input and output operation comprising generating plural kinds of offset addresses corresponding, respectively, to the plural kinds of signal processing and not overlapping with each other, generating at least one write address or read address for the sampled data for each of the plural kinds of signal processing by modifying the basic address by at least one of the offset addresses corresponding to each of the plural kinds of signal processing, and delivering the generated at least one write address or read address to the storage device.

摘要翻译： 提供一种数字信号处理器和数字信号处理方法，其能够执行多种信号处理，并且还执行用与少量硬件的各种信号处理相对应的方式存储采样数据的处理，即使在 存储和读取相对于存储器件处理的采样数据的方式在多种信号处理之间是不同的情况。 存储装置将分别对应于多种信号处理的多种采样数据进行存储。 计数器在每个采样周期更新其计数值，并生成更新的计数值作为基本地址。 采样数据输入和输出装置在每个采样周期执行输入和输出操作，所述输入和输出操作包括产生分别对应于多种信号处理并且彼此不重叠的多种偏移地址，至少产生 通过对应于多种信号处理中的每一种的偏移地址中的至少一个来修改基本地址，并且将所生成的至少一个信号处理中的至少一个传送给多个信号处理中的每一个的采样数据的一个写入地址或读取地址 向存储设备写入地址或读取地址。

公开(公告)号：US06263036B1

公开(公告)日：2001-07-17

申请号：US09124752

申请日：1998-07-29

申请人： Yusuke Yamamoto ,  Ichiro Futohashi ,  Yasuyuki Muraki

发明人： Yusuke Yamamoto ,  Ichiro Futohashi ,  Yasuyuki Muraki

IPC分类号： H04L2500

CPC分类号： G06F5/14 ,  G06F2205/061 ,  H03H17/0628

摘要： An asynchronous signal input apparatus includes a memory device which writes data that are input at a predetermined frequency, in response to a write signal, and reads data in response to a read signal. A data quantity measuring device measures a data quantity representing a quantity of data stored in the memory device. A read signal generating device generates the read signal at a frequency that varies depending upon the measured data quantity. A sampling frequency conversion apparatus comprises the memory device, data quantity measuring device, and read signal generating device employed in the asynchronous signal input apparatus. Further, the read signal generating device includes a converter which performs non-linear conversion on the data quantity measured by the data quantity measuring device. An interpolation information producing device produces interpolation information to be used for data generated from the memory device, based on the data quantity to which the non-linear gain is given by the converter. An interpolation device interpolates data that are read from the memory device in response to the read signal, based on the produced interpolation information.

摘要翻译： 异步信号输入装置包括响应于写信号写入以预定频率输入的数据的存储装置，并响应于读信号读取数据。 数据量测量装置测量表示存储在存储装置中的数据量的数据量。 读取信号产生装置以取决于测量数据量而变化的频率产生读取信号。 采样频率转换装置包括在异步信号输入装置中采用的存储装置，数据量测量装置和读信号产生装置。 此外，读信号生成装置包括对由数据量测量装置测量的数据量执行非线性转换的转换器。 内插信息产生装置基于由转换器给出非线性增益的数据量，产生用于从存储装置生成的数据的内插信息。 内插装置根据所生成的插值信息，内插根据读取信号从存储装置读出的数据。

公开(公告)号：US06360328B1

公开(公告)日：2002-03-19

申请号：US09301914

申请日：1999-04-29

申请人： Yasuyuki Muraki ,  Yusuke Yamamoto

发明人： Yasuyuki Muraki ,  Yusuke Yamamoto

IPC分类号： G06F104

CPC分类号： G06F1/324 ,  G06F1/3203 ,  Y02D10/126

摘要： A digital signal processor performs signal processing corresponding to a designated one of a plurality of sampling frequencies. A slot changing device carries out changeover of slots at a frequency equivalent to a common multiple of the plurality of sampling frequencies. A slot cycle setting device sets a slot cycle formed of the slots corresponding in number to a sampling period determined by the designated one of the plurality of sampling frequencies. An executing device executes routines corresponding to the slots forming the slot cycle, with a repetition period determined by the set slot cycle, to thereby perform signal processing corresponding to the designated one of the plurality of sampling frequencies in a time-discrete manner.

摘要翻译： 数字信号处理器执行与多个采样频率中指定的采样频率相对应的信号处理。 时隙切换装置以等于多个采样频率的公倍数的频率执行时隙的切换。 时隙周期设置装置将由数量相对应的时隙形成的时隙周期设置为由多个采样频率中指定的采样频率确定的采样周期。 执行装置执行与形成时隙周期的时隙相对应的程序，具有由所设定的时隙周期确定的重复周期，从而以时间离散的方式执行与多个采样频率中指定的一个采样频率相对应的信号处理。

公开(公告)号：US06513123B2

公开(公告)日：2003-01-28

申请号：US09912874

申请日：2001-07-25

申请人： Yasuyuki Muraki ,  Yusuke Yamamoto

发明人： Yasuyuki Muraki ,  Yusuke Yamamoto

IPC分类号： G06F132

CPC分类号： G06F1/324 ,  G06F1/3203 ,  Y02D10/126

摘要： The present invention is directed to a power control circuit for reducing wasteful power consumption of an electronic apparatus such as a digital signal processor. More specifically, a preferred embodiment of the present invention includes a processing detecting device that detects occurrence of an index indicative of a start of execution of a process by the electronic apparatus, a processing termination detecting device for detecting a termination of the processes, and a power control device that responds to the detection of the termination of the process for reducing the power consumption by at least one circuit element of the electronic apparatus for a time period after the termination of the processing, and until the next occurrence of the index indicative of another start of execution of a process.

摘要翻译： 本发明涉及一种用于减少诸如数字信号处理器之类的电子设备的浪费的功率消耗的功率控制电路。 更具体地说，本发明的优选实施例包括处理检测装置，其检测指示由电子装置执行处理的开始的指标的发生，用于检测处理的终止的处理终止检测装置，以及 功率控制装置，其响应于终止处理的终止的检测，以在处理结束之后的一段时间内减少电子设备的至少一个电路元件的功率消耗，并且直到下一次发生指示 另一个进程的执行开始。

公开(公告)号：US06397321B1

公开(公告)日：2002-05-28

申请号：US09362950

申请日：1999-07-28

申请人： Yusuke Yamamoto ,  Yasuyuki Muraki

发明人： Yusuke Yamamoto ,  Yasuyuki Muraki

IPC分类号： G06F9318

CPC分类号： G06F9/3853 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30083 ,  G06F9/30185 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/171 ,  Y02D50/20

摘要： A digital signal processor which can reduce the electric power consumption in a fine manner according to the contents of processing to be executed. An arithmetic device performs arithmetic operations according to operation instructions. A storage device stores plural sets of the operation instructions and control instructions corresponding to respective ones of the operation instructions and indicative of kinds of processings to be executed according to the respective ones of the operation instructions. A control device is disposed to receive an externally supplied control signal indicative of kinds of processings to be executed by the digital signal processor, and reads out the operation instructions and the control instructions corresponding to the respective ones of the operation instructions and renders the arithmetic device inoperative when a kind of processing indicated by the control signal and a kind of processing indicated by each of the control instructions read out do not coincide with each other.

摘要翻译： 一种数字信号处理器，其可以根据要执行的处理的内容以精细的方式降低电力消耗。 算术装置根据操作指令进行算术运算。 存储装置存储多组操作指令和对应于操作指令的相应操作指令的控制指令，并指示要根据操作指令的相应操作执行的处理的种类。 控制装置被设置为接收指示要由数字信号处理器执行的处理种类的外部提供的控制信号，并且读出与各操作指令相对应的操作指令和控制指令，并且使运算装置 当由控制信号指示的一种处理和每个读出的控制指令所指示的一种处理不一致时，不起作用。

公开(公告)号：US07590460B2

公开(公告)日：2009-09-15

申请号：US10976117

申请日：2004-10-28

申请人： Naotoshi Nishioka ,  Hiroyuki Toda ,  Yasuyuki Muraki

发明人： Naotoshi Nishioka ,  Hiroyuki Toda ,  Yasuyuki Muraki

IPC分类号： G06F17/00

CPC分类号： G11B27/031 ,  G10H2230/041 ,  G11B20/10527 ,  G11B2020/10555 ,  G11B2020/10574

摘要： An audio signal processor is composed of a data path unit, a mode register and a state machine unit. The data path unit applies one or more arithmetical operation to an audio signal for performing signal processing of the audio signal. The mode register stores mode information specifying the signal processing to be performed by the data path unit. The state machine unit sequentially feeds control signals according to the mode information for enabling the data path unit to apply one or more arithmetical operation to the audio signal so as to perform the signal processing. The performed signal processing is composed of the one or more arithmetical operations, and is specified by the mode information stored in the mode register.

摘要翻译： 音频信号处理器由数据路径单元，模式寄存器和状态机单元组成。 数据路径单元对音频信号应用一个或多个算术运算，以执行音频信号的信号处理。 模式寄存器存储指定要由数据路径单元执行的信号处理的模式信息。 状态机单元根据模式信息依次馈送控制信号，以使数据路径单元能够对音频信号应用一个或多个算术运算，以执行信号处理。 执行的信号处理由一个或多个算术运算组成，并由存储在模式寄存器中的模式信息指定。

公开(公告)号：US20050138275A1

公开(公告)日：2005-06-23

申请号：US10986525

申请日：2004-11-10

申请人： Yasuyuki Muraki

发明人： Yasuyuki Muraki

IPC分类号： G06F12/00 ,  G11C11/4072

CPC分类号： G06F9/4403

摘要： A digital signal processor is adapted to a working RAM, which is capable of storing a plurality of data in a rewritable manner and whose storage area is divided into a plurality of sub-areas that are designated by addresses in read/write operations, wherein an operation circuit performs calculations on the data of the working RAM in accordance with a program, and wherein upon detection of a non-access event in which the program does not need to access the working RAM, a write circuit compulsorily writes ‘0’ into the working RAM with regard to each of the prescribed addresses of the prescribed sub-areas subjected to initialization, which are designated by address data. Thus, it is possible to actualize the selective initialization on the prescribed sub-areas within the working RAM without increasing the scale of the peripheral circuitry, without requiring complicated controls, and without increasing the overall processing time therefor.

摘要翻译： 数字信号处理器适用于工作RAM，其能够以可重写的方式存储多个数据，并且其存储区域被划分为在读/写操作中由地址指定的多个子区域，其中， 操作电路根据程序对工作RAM的数据执行计算，并且其中当检测到程序不需要访问工作RAM的非访问事件时，写电路强制将“0”写入到 关于由地址数据指定的经过初始化的规定子区域的规定地址的每个规定地址的工作RAM。 因此，可以在不增加外围电路的规模的情况下实现工作RAM内的规定子区域的选择性初始化，而不需要复杂的控制，并且不增加其整体处理时间。

公开(公告)号：US07492289B2

公开(公告)日：2009-02-17

申请号：US11687207

申请日：2007-03-16

申请人： Yasuyuki Muraki

发明人： Yasuyuki Muraki

IPC分类号： H03M7/00

CPC分类号： H03H17/0223 ,  H03H17/045 ,  H03H2017/0298

摘要： Periodically sampled digital data (e.g., digital audio data) are once stored in a work RAM and are then subjected to signal processing such as arithmetic operations using coefficients. A primary accumulator register stores results of arithmetic operations. A secondary accumulator register is specialized in handling a relatively high processing load (e.g., down-sampling) having a plurality of steps, which are distributed and appropriately assigned to a plurality of periods in response to output timings. In order to execute other processing in each period, intermediate results of arithmetic operations regarding the relatively high processing load are temporarily stored in the secondary accumulator register. The number of steps assigned to each period is appropriately changed in response to interruption of the other processing, whereas the relatively high processing load is given a first priority in comparison with the other processing.

摘要翻译： 定期采集的数字数据（例如，数字音频数据）一旦被存储在工作RAM中，然后进行信号处理，例如使用系数的算术运算。 主累加器寄存器存储算术运算结果。 辅助累加器寄存器专门处理具有多个步骤的相对较高的处理负载（例如，下采样），其响应于输出定时被分布并适当地分配给多个周期。 为了在每个周期执行其他处理，关于相对较高的处理负荷的算术运算的中间结果被临时存储在次级累加器寄存器中。 分配给每个周期的步骤的数量响应于其他处理的中断而适当地改变，而相对于其他处理，相对较高的处理负载被赋予第一优先级。

公开(公告)号：US07247784B2

公开(公告)日：2007-07-24

申请号：US10344806

申请日：2001-08-17

申请人： Yasuyuki Muraki ,  Ichiro Futohashi

发明人： Yasuyuki Muraki ,  Ichiro Futohashi

IPC分类号： A63H5/00

CPC分类号： G10H7/004 ,  G10H1/0058 ,  G10H2230/021 ,  G10H2230/041 ,  G10H2240/056 ,  G10H2240/061 ,  G10H2240/251 ,  G10H2240/311 ,  G10H2250/585 ,  G10H2250/595 ,  H04M1/72519

摘要： There are provided a musical tone-generating apparatus which neither requires hardware having an increased circuit size nor imposes a heavy burden on a CPU thereof, and a mobile terminal apparatus including the musical tone-generating apparatus, as well as a musical tone-generating method, and a storage medium storing a program for executing the method. A CPU converts music contents data stored in a RAM to hardware tone generator control data, stores the resulting data into the RAM. In reproduction, the CPU reads out and sends the hardware tone generator control data to a hardware tone generator. A data decoder circuit of the hardware tone generator sequentially reads out the hardware tone generator control data from a FIFO and separates the read data into time management information and data of a parameter for generation of a musical tone, and sets the time management information to a counter. Under the control of the counter performing the time management, a register write controller writes data of the parameter into a tone generator control register at timing indicated by the time management information. A tone generator section produces the musical tone based on the data stored in the tone generator control register.

摘要翻译： 提供了一种既不需要具有增加的电路尺寸的硬件也不对其CPU施加沉重负担的音乐产生装置，以及包括乐音产生装置的移动终端装置以及乐音产生方法 以及存储用于执行该方法的程序的存储介质。 CPU将存储在RAM中的音乐内容数据转换为硬件音调发生器控制数据，将得到的数据存储到RAM中。 在再现时，CPU读出并将硬件乐音发生器控制数据发送到硬件乐音发生器。 硬件音调发生器的数据解码器电路从FIFO顺序地读出硬件音调发生器控制数据，并将读取的数据分离成时间管理信息和用于产生音调的参数的数据，并将时间管理信息设置为 计数器。 在执行时间管理的计数器的控制下，寄存器写入控制器在时间管理信息指示的定时将数据的数据写入音调发生器控制寄存器。 乐音发生器部分基于存储在乐音发生器控制寄存器中的数据产生乐音。

公开(公告)号：US08346830B2

公开(公告)日：2013-01-01

申请号：US12255588

申请日：2008-10-21

申请人： Yasuyuki Muraki

发明人： Yasuyuki Muraki

IPC分类号： G06F7/523

CPC分类号： G06F7/5443 ,  G06F9/30014 ,  G06F9/30112 ,  G06F2207/3816

摘要： Register includes flip-flop circuits each constructed to retain data of n bit in synchronism with a clock pulse, the register retaining a multiplication result of a multiplier dividedly by the flip-flop circuits, n bit per flip-flop circuit. For each of a first and second numeric value data to be multiplied by the multiplier, a control circuit detects the number of consecutive zeros from the lowest-order bit of the data and performs control, on the basis of the detected number of the consecutive zeros and for each flip-flop circuit, as to whether or not the clock pulse should be supplied to the flip-flop circuit. The control circuit obtains an integral quotient value x by dividing by the number n the sum between the detected numbers for the first and second numeric value data, to stop the clock pulse supply to a particular number x of flip-flop circuit counted from the lowest-order.

摘要翻译： 寄存器包括触发器电路，每个触发器电路被构造为保持与时钟脉冲同步的n位的数据，寄存器保持乘法器的乘法结果，由触发器电路分开，每个触发器电路为n位。 对于要乘以乘数的第一和第二数值数据中的每一个，控制电路根据检测到的连续零的数量来检测来自数据的最低位的连续零的数量，并执行控制 并且对于每个触发器电路，是否应该将时钟脉冲提供给触发器电路。 控制电路通过将数字n除以第一和第二数值数据的检测号之和来获得积分商值x，以将时钟脉冲供应停止到从最低的数字计数的触发器电路的特定数量x -订购。