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公开(公告)号：US20090002208A1
公开(公告)日：2009-01-01
申请号：US12009736
申请日：2008-01-22
Applicant: Naotoshi Nishioka
Inventor： Naotoshi Nishioka
IPC: H03M7/00
CPC classification number: H03H15/02
Abstract: In a sampling frequency conversion apparatus, an input sample register stores a predetermined number of input samples as an original sequence of input samples for an interpolative operation. A coefficient generating part prepares a first sequence of interpolative coefficients corresponding to an oversampled sequence of input samples which are obtained by inserting nominal input samples of zero values to the input samples stored in the input sample register, and generates a second sequence of interpolative coefficients which are extracted from the first sequence of the interpolative coefficients and which correspond to the original sequence of the input samples. A convolutional operation part convolutes the second sequence of the interpolative coefficients with the original sequence of the input samples so as to output an interpolated sample.
Abstract translation: 在采样频率转换装置中，输入采样寄存器将预定数量的输入采样存储为用于内插操作的输入采样的原始序列。 系数生成部分准备与通过将零值的标称输入样本插入到存储在输入样本寄存器中的输入样本而获得的输入样本的过采样序列相对应的内插系数的第一序列，并生成第二序列的内插系数， 从内插系数的第一序列中提取，并且对应于输入样本的原始序列。 卷积运算部分将内插系数的第二序列与输入样本的原始序列进行卷积，以便输出插值样本。
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公开(公告)号：US07185122B2
公开(公告)日：2007-02-27
申请号：US10762667
申请日：2004-01-22
Applicant: Naotoshi Nishioka
Inventor： Naotoshi Nishioka
CPC classification number: G06F13/28
Abstract: A data transfer control device and method is devoted to control data transfer (i.e., DMA transfer) between a main memory whose storage capacity is arbitrarily set and a buffer memory (e.g., a FIFO memory) incorporated in a peripheral module, wherein a first register is arranged to store a first value representing a first number of times for transferring m-bit data to suit the storage capacity of the buffer memory, and a second register is arranged to store a second value representing a second number of times for transferring m-bit data to match the amount of transferring data stored in the main memory. A controller is arranged to control transferring of m-bit data based on the first value while controlling writing operations for the buffer memory. It determines the timing to output an interrupt signal to a CPU managing the main memory on the basis of the second value.
Abstract translation: 一种数据传输控制装置和方法，用于控制任意设置存储容量的主存储器与并入外围模块的缓冲存储器（例如，FIFO存储器）之间的数据传输（即DMA传输），其中第一寄存器 被布置为存储表示用于传送m位数据以适应缓冲存储器的存储容量的第一次数的第一值，并且第二寄存器被布置为存储表示用于传送m位数据的第二次数的第二值， 位数据以匹配存储在主存储器中的传送数据量。 控制器被布置为在控制缓冲存储器的写入操作的同时基于第一值来控制m位数据的传送。 它基于第二个值确定将中断信号输出到管理主存储器的CPU的定时。
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公开(公告)号：US07031207B2
公开(公告)日：2006-04-18
申请号：US10829523
申请日：2004-04-22
Applicant: Naotoshi Nishioka
Inventor： Naotoshi Nishioka
IPC: G11C7/00
CPC classification number: G11C7/1093 , G11C7/06 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C2207/065 , G11C2207/2281 , G11C2207/229
Abstract: A semiconductor memory device has an array of memory cells for memorizing data, an address circuit responsive to an address signal for addressing a memory cell in the array, and a write circuit responsive to a write signal for writing the data into the addressed memory cell. A control circuit is provided for delaying an input timing of the write signal to the write circuit by a given delay amount so as to adjust a timing of writing the data after addressing the memory cell. The control circuit has a register and a variable delay. The register is capable of registering control data for setting the delay amount. The variable delay is provided for delaying the write signal by the set delay amount and outputting the delayed write signal to the write circuit.
Abstract translation: 半导体存储器件具有用于存储数据的存储器单元阵列，响应于用于寻址阵列中的存储器单元的地址信号的地址电路，以及响应于用于将数据写入寻址的存储单元的写入信号的写入电路。 提供一种控制电路，用于将写入信号的输入定时延迟给写入电路一个给定的延迟量，以便在寻址存储单元之后调整写入数据的定时。 控制电路具有寄存器和可变延迟。 寄存器能够注册用于设置延迟量的控制数据。 提供可变延迟用于将写入信号延迟设定的延迟量并将延迟的写入信号输出到写入电路。
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公开(公告)号：US07590460B2
公开(公告)日：2009-09-15
申请号：US10976117
申请日：2004-10-28
Applicant: Naotoshi Nishioka , Hiroyuki Toda , Yasuyuki Muraki
Inventor： Naotoshi Nishioka , Hiroyuki Toda , Yasuyuki Muraki
IPC: G06F17/00
CPC classification number: G11B27/031 , G10H2230/041 , G11B20/10527 , G11B2020/10555 , G11B2020/10574
Abstract: An audio signal processor is composed of a data path unit, a mode register and a state machine unit. The data path unit applies one or more arithmetical operation to an audio signal for performing signal processing of the audio signal. The mode register stores mode information specifying the signal processing to be performed by the data path unit. The state machine unit sequentially feeds control signals according to the mode information for enabling the data path unit to apply one or more arithmetical operation to the audio signal so as to perform the signal processing. The performed signal processing is composed of the one or more arithmetical operations, and is specified by the mode information stored in the mode register.
Abstract translation: 音频信号处理器由数据路径单元，模式寄存器和状态机单元组成。 数据路径单元对音频信号应用一个或多个算术运算，以执行音频信号的信号处理。 模式寄存器存储指定要由数据路径单元执行的信号处理的模式信息。 状态机单元根据模式信息依次馈送控制信号，以使数据路径单元能够对音频信号应用一个或多个算术运算，以执行信号处理。 执行的信号处理由一个或多个算术运算组成，并由存储在模式寄存器中的模式信息指定。
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公开(公告)号：US07570727B2
公开(公告)日：2009-08-04
申请号：US11355638
申请日：2006-02-15
Applicant: Takayoshi Mochizuki , Naotoshi Nishioka
Inventor： Takayoshi Mochizuki , Naotoshi Nishioka
CPC classification number: H04H20/95 , G06F5/12 , G06F2205/061 , H04J3/062 , H04L7/0041 , H04L7/005
Abstract: In a data transmission controller apparatus, a first-in first-out storage stores newly inputted data in response to a write request signal, and reads and outputs the stored data which has been stored earliest in response to a read request signal. A remaining data amount detection portion detects a remaining data amount of the stored data which remain in the first-in first-out storage. A variable frequency oscillating portion generates an enable signal at a time rate according to frequency control information so as to enable generation of the write request signal or read request signal. A frequency control portion corrects the frequency control information so as to return the remaining data amount to an appropriate value when the remaining data amount detected by the remaining data amount detection portion varies away from the appropriate value toward an upper limit value or varies away from the appropriate value toward a lower limit value.
Abstract translation: 在数据传输控制器装置中，先进先出存储器响应于写入请求信号存储新输入的数据，并且响应于读取请求信号读取并输出已经被最早存储的存储的数据。 剩余数据量检测部分检测保持在先进先出存储中的存储数据的剩余数据量。 可变频率振荡部分根据频率控制信息以时间速率产生使能信号，以便能够产生写入请求信号或读取请求信号。 当由剩余数据量检测部分检测到的剩余数据量从适当值向上限值变化时，频率控制部分校正频率控制信息，以便将剩余数据量返回到适当值，或者从 适合下限值的值。
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Patent Agency Ranking
6.发明授权公开(公告)号：US07450678B2
公开(公告)日：2008-11-11
申请号：US10999884
申请日：2004-11-30
Applicant: Naotoshi Nishioka
Inventor： Naotoshi Nishioka
CPC classification number: H03H17/0628
Abstract: In an asynchronous data input apparatus, a writing section writes data successively into a FIFO buffer memory at an variable input rate so that the data are accumulated in the FIFO buffer memory. A reading section reads the accumulated data successively from the FIFO buffer memory at an variable output rate so that the data amount residing in the FIFO buffer memory varies temporally. A detector detects a current data amount residing in the FIFO buffer memory, and a current direction of variation of the data amount residing in the FIFO buffer memory. A loop filter generates control information according to both of the detected current data amount and the detected current direction of variation of the data amount. A controller regulates the output rate according to the control information so as to promptly converge the current data amount residing in the FIFO buffer memory to a target data amount.
Abstract translation: 在异步数据输入装置中，写入部分以可变输入速率将数据连续地写入FIFO缓冲存储器，使得数据被累积在FIFO缓冲存储器中。 读取部分以可变输出速率从FIFO缓冲存储器连续地读取累积数据，使得驻留在FIFO缓冲存储器中的数据量在时间上变化。 检测器检测驻留在FIFO缓冲存储器中的当前数据量以及驻留在FIFO缓冲存储器中的数据量的当前变化方向。 环路滤波器根据检测到的当前数据量和检测到的数据量的变化的当前方向两者来生成控制信息。 控制器根据控制信息调节输出速率，以便将驻留在FIFO缓冲存储器中的当前数据量迅速收敛到目标数据量。
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7.发明申请公开(公告)号：US20050141033A1
公开(公告)日：2005-06-30
申请号：US10999884
申请日：2004-11-30
Applicant: Naotoshi Nishioka
Inventor： Naotoshi Nishioka
CPC classification number: H03H17/0628
Abstract: In an asynchronous data input apparatus, a writing section writes data successively into a FIFO buffer memory at an variable input rate so that the data are accumulated in the FIFO buffer memory. A reading section reads the accumulated data successively from the FIFO buffer memory at an variable output rate so that the data amount residing in the FIFO buffer memory varies temporally. A detector detects a current data amount residing in the FIFO buffer memory, and a current direction of variation of the data amount residing in the FIFO buffer memory. A loop filter generates control information according to both of the detected current data amount and the detected current direction of variation of the data amount. A controller regulates the output rate according to the control information so as to promptly converge the current data amount residing in the FIFO buffer memory to a target data amount.
Abstract translation: 在异步数据输入装置中，写入部分以可变输入速率将数据连续地写入FIFO缓冲存储器，使得数据被累积在FIFO缓冲存储器中。 读取部分以可变输出速率从FIFO缓冲存储器连续地读取累积数据，使得驻留在FIFO缓冲存储器中的数据量在时间上变化。 检测器检测驻留在FIFO缓冲存储器中的当前数据量以及驻留在FIFO缓冲存储器中的数据量的当前变化方向。 环路滤波器根据检测到的当前数据量和检测到的数据量的变化的当前方向两者来生成控制信息。 控制器根据控制信息来调节输出速率，以便将驻留在FIFO缓冲存储器中的当前数据量迅速收敛到目标数据量。
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公开(公告)号：US20050096766A1
公开(公告)日：2005-05-05
申请号：US10976117
申请日：2004-10-28
Applicant: Naotoshi Nishioka , Hiroyuki Toda , Yasuyuki Muraki
Inventor： Naotoshi Nishioka , Hiroyuki Toda , Yasuyuki Muraki
CPC classification number: G11B27/031 , G10H2230/041 , G11B20/10527 , G11B2020/10555 , G11B2020/10574
Abstract: An audio signal processor is composed of a data path unit, a mode register and a state machine unit. The data path unit applies one or more arithmetical operation to an audio signal for performing signal processing of the audio signal. The mode register stores mode information specifying the signal processing to be performed by the data path unit. The state machine unit sequentially feeds control signals according to the mode information for enabling the data path unit to apply one or more arithmetical operation to the audio signal so as to perform the signal processing. The performed signal processing is composed of the one or more arithmetical operations, and is specified by the mode information stored in the mode register.
Abstract translation: 音频信号处理器由数据路径单元，模式寄存器和状态机单元组成。 数据路径单元对音频信号应用一个或多个算术运算，以执行音频信号的信号处理。 模式寄存器存储指定要由数据路径单元执行的信号处理的模式信息。 状态机单元根据模式信息依次馈送控制信号，以使数据路径单元能够对音频信号应用一个或多个算术运算，以执行信号处理。 执行的信号处理由一个或多个算术运算组成，并由存储在模式寄存器中的模式信息指定。
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公开(公告)号：US06345010B2
公开(公告)日：2002-02-05
申请号：US09754132
申请日：2001-01-05
Applicant: Yasuhisa Shimazaki , Kenichi Osada , Hiroshi Maruyama , Naotoshi Nishioka
Inventor： Yasuhisa Shimazaki , Kenichi Osada , Hiroshi Maruyama , Naotoshi Nishioka
IPC: G11C800
CPC classification number: G11C7/18 , G11C11/419
Abstract: A semiconductor storage device controls crosstalk of write data to read data during reading and writing operations performed in the same cycle. The device has a plurality of word lines WL, a plurality of bit lines LBL, memory cells CELL which are connected to the word lines and the bit lines, reading global bit lines RGBL connected to a sense amplifier SA and writing global bit lines WBGL connected to a write amplifier WA. A selection circuit YSWn selectively connects the reading and writing global bit lines with the local bit lines. For first and second writing global bit lines arranged between first and second reading global bit lines, a distance between the first writing global bit line and the first reading global bit line, or a distance between the second writing global bit line and the second reading global bit line being is longer than a distance between the first and second writing global bit lines. Alternatively, the writing and reading global bit lines are formed in different wiring layers in the substrate of the device.
Abstract translation: 半导体存储装置控制在同一周期中执行的读写操作期间写入数据的串扰以读取数据。 该器件具有多个字线WL，多个位线LBL，连接到字线和位线的存储单元CELL，读取连接到读出放大器SA的全局位线RGBL，并连接全局位线WBGL 写入放大器WA。 选择电路YSWn选择性地将读写全局位线与本地位线连接。 对于布置在第一和第二读取全局位线之间的第一和第二写入全局位线，第一写入全局位线和第一读取全局位线之间的距离，或者第二写入全局位线和第二读取全局位线之间的距离 位线长于第一和第二写入全局位线之间的距离。 或者，写入和读取全局位线形成在器件的衬底中的不同布线层中。
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公开(公告)号：US07609181B2
公开(公告)日：2009-10-27
申请号：US12009736
申请日：2008-01-22
Applicant: Naotoshi Nishioka
Inventor： Naotoshi Nishioka
IPC: H03M7/00
CPC classification number: H03H15/02
Abstract: In a sampling frequency conversion apparatus, an input sample register stores a predetermined number of input samples as an original sequence of input samples for an interpolative operation. A coefficient generating part prepares a first sequence of interpolative coefficients corresponding to an oversampled sequence of input samples which are obtained by inserting nominal input samples of zero values to the input samples stored in the input sample register, and generates a second sequence of interpolative coefficients which are extracted from the first sequence of the interpolative coefficients and which correspond to the original sequence of the input samples. A convolutional operation part convolutes the second sequence of the interpolative coefficients with the original sequence of the input samples so as to output an interpolated sample.
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