公开(公告)号：US20100001797A1

公开(公告)日：2010-01-07

申请号：US12091417

申请日：2006-08-02

申请人： Kazuhisa Ishiguro ,  Yoshiaki Takahashi

发明人： Kazuhisa Ishiguro ,  Yoshiaki Takahashi

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F2203/45364

摘要： A differential amplifier circuit at the input stage is configured with a twin differential type having a first differential amplifier circuit (11) and a second differential amplifier circuit (12), respective outputs of which are received by a first and a second source-grounded amplifier (M5, M10). The second source-grounded amplifier (M10) is connected to a current mirror circuit (M11, M12), which is driven by the drain current of the second source-grounded amplifier (M10). With this configuration, the dynamic range for the upper half portion of an alternating signal output from an output terminal (OUT) is determined by the current supply capability of the first source-grounded amplifier (M5) and the dynamic range for the lower half portion is determined by the current supply capability of the second source-grounded amplifier (M10). This eliminates the need of a constant current circuit of a large current for generating a signal having lower half portion in which the waveform distortion is improved.

摘要翻译： 输入级的差分放大器电路配置有具有第一差分放大器电路（11）和第二差分放大器电路（12）的双差分型，其各自的输出由第一和第二源极接地放大器 （M5，M10）。 第二源极接地放大器（M10）连接到由第二源极接地放大器（M10）的漏极电流驱动的电流镜电路（M11，M12）。 利用这种配置，从输出端子（OUT）输出的交流信号的上半部分的动态范围由第一源极接地放大器（M5）的电流供应能力和下半部分的动态范围 由第二源极接地放大器（M10）的电流供应能力确定。 这消除了用于产生具有其中波形失真提高的下半部分的信号的大电流的恒流电路的需要。

公开(公告)号：US20090298454A1

公开(公告)日：2009-12-03

申请号：US12295912

申请日：2006-11-08

申请人： Takeshi Ikeda ,  Hiroshi Miyagi

发明人： Takeshi Ikeda ,  Hiroshi Miyagi

IPC分类号： H04B1/16 ,  H04B1/26

CPC分类号： H03G3/3068 ,  H04B1/001

摘要： By A/D converting a signal output from a mixer (4) and inputting the A/D converted signal to a DSP (8), and generating AGC control data (DL) corresponding to a level of the signal to control a gain of an LNA (3) in such a manner that a voltage input to an A/D converting circuit (7) is lower than a full scale voltage of the A/D converting circuit (7), it is possible to prevent a signal having an excessively high level beyond a dynamic range of the A/D converting circuit (7) from being input to the A/D converting circuit (7). By controlling the gain of the LNA (3) corresponding to a level of a broad band signal before passing through a BPF (11) and controlling a gain of an IF amplifier (12) corresponding to a level of a narrow band signal after passing through the BPF (11), moreover, it is possible to properly control a gain of an AGC as a whole in consideration of signal levels of both a desirable wave and a disturbing wave.

摘要翻译： 通过A / D转换从混频器（4）输出的信号并将A / D转换的信号输入到DSP（8），并产生对应于信号电平的AGC控制数据（DL）以控制一个 LNA（3），使得输入到A / D转换电路（7）的电压低于A / D转换电路（7）的满量程电压，可以防止过度的信号 高于A / D转换电路（7）的动态范围的输入到A / D转换电路（7）的高电平。 通过在通过BPF（11）之前控制对应于宽频带信号的电平的LNA（3）的增益，并且控制与通过后的窄频带信号的电平相对应的IF放大器（12）的增益 BPF（11），此外，考虑到期望的波和干扰波的信号电平，可以整体地适当地控制AGC的增益。

公开(公告)号：US20090268916A1

公开(公告)日：2009-10-29

申请号：US12067164

申请日：2006-06-27

申请人： Hiroshi Miyagi

发明人： Hiroshi Miyagi

IPC分类号： H04H20/48

CPC分类号： H03C3/40 ,  H03C5/00 ,  H04H20/48

摘要： An FM transmitter improved in degree of freedom of selecting components. The FM transmitter comprises an oscillator 72 connected to a crystal oscillator 70, a clock generating circuit 50 for generating a clock signal having a frequency which is an integral multiple of the frequency of the output signal from the oscillator 72 by using the output signal as a reference frequency signal fr1, a DSP 20 operable synchronously with the clock signal and adapted for conducting digital stereo modulation, digital FM modulation, and digital IQ modulation of inputted stereo data, a frequency synthesizer 60 for generating a signal having a frequency which is an integral multiple of the frequency of the output signal from the oscillator 72 by using the output signal as a reference frequency signal fr2, mixers 40, 42 for mixing the signals outputted from the DSP 20 with the signal generated by the frequency synthesizer 60, an adder 44 for adding the outputs from the mixers 40, 42, and amplifier 46 for amplifying the output signal from the adder 44 to transmit it from an antenna 48.

摘要翻译： FM发射机在选择部件的自由度方面有所改进。 FM发射机包括连接到晶体振荡器70的振荡器72，时钟产生电路50，用于通过使用输出信号产生具有来自振荡器72的输出信号的频率的整数倍的频率的时钟信号 参考频率信号fr1，与时钟信号同步操作的DSP 20，用于进行数字立体声调制，数字FM调制和输入的立体声数据的数字IQ调制;频率合成器60，用于产生频率为积分的信号 通过使用输出信号作为参考频率信号fr2，来自振荡器72的输出信号的频率的倍数，用于将从DSP 20输出的信号与由频率合成器60产生的信号混合的混频器40,42，加法器44 用于添加来自混频器40,42和放大器46的输出，用于放大来自加法器44的输出信号，以从蚂蚁 enna 48。

公开(公告)号：US07602248B2

公开(公告)日：2009-10-13

申请号：US12092523

申请日：2006-07-12

申请人： Kazuhisa Ishiguro

发明人： Kazuhisa Ishiguro

IPC分类号： H03F3/45

CPC分类号： H03F1/0261 ,  H03F1/308 ,  H03F3/301 ,  H03F3/3022 ,  H03F3/303 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2203/30061 ,  H03F2203/45596 ,  H03F2203/45726

摘要： An idling current setting circuit (3) includes: current setting transistors (Q3, Q4) connected to output transistors (Q1, Q2) in a driver (2) in current mirror form; a plurality of current setting resistors (R1 to R4); and a plurality of switches (ASW1 to ASW4) for switching to any of the current setting resistors (R1 to R4). This enables the idling current to be set by the current mirror ratio between the current setting transistors (Q3, Q4) having no connection with the open gain of the power amplifier and the output transistors (Q1, Q2), so that the idling current can be arbitrarily set independently of the open gain.

摘要翻译： 怠速电流设定电路（3）包括：以电流镜面形式连接到驱动器（2）中的输出晶体管（Q1，Q2）的电流设定晶体管（Q3，Q4） 多个电流设定电阻（R1〜R4）; 以及用于切换到任何电流设定电阻器（R1〜R4）的多个开关（ASW1〜ASW4）。 这使得能够通过与功率放大器和输出晶体管（Q1，Q2）的开放增益无关的电流设定晶体管（Q3，Q4）之间的电流镜比来设定怠速电流，使得空转电流可以 可以独立于开放增益任意设置。

公开(公告)号：US20090225990A1

公开(公告)日：2009-09-10

申请号：US11908602

申请日：2006-04-25

申请人： Hiroshi Miyagi

发明人： Hiroshi Miyagi

IPC分类号： H04H20/48 ,  H03L7/08

CPC分类号： H03L7/183

摘要： A clock generating circuit having a simple constitution and an audio system are disclosed.The clock generating circuit (300) comprises an oscillator (12) for generating a reference frequency signal by means of a crystal oscillator (10) of a resonance frequency of 32.768 kHz, a PLL circuit for generating a signal synchronizing with the reference frequency signal generated by the oscillator (12) and having a frequency which is M times the reference frequency signal, a first frequency divider (30) for generating a first clock signal (CLK1) having a frequency of 32 kHz by frequency-dividing the signal generated by the PLL circuit at a division ratio N1, a second frequency divider (32) for generating a second clock signal (CLK2) having a frequency of 38 kHz by frequency-dividing the signal generated by the PLL circuit at a division ratio N2, and a third frequency divider (34) for generating a third clock signal (CLK3) having a frequency of 48 kHz by frequency-dividing the signal generated by the PLL circuit at a division ratio N3.

摘要翻译： 公开了一种具有简单结构和音频系统的时钟发生电路。 时钟发生电路（300）包括：振荡器（12），用于通过共振频率为32.768kHz的晶体振荡器（10）产生参考频率信号; PLL电路，用于产生与产生的参考频率信号同步的信号 通过所述振荡器（12）并且具有所述参考频率信号的M倍的频率的第一分频器（30），用于通过对由所述基准频率信号产生的信号进行分频来产生具有32kHz频率的第一时钟信号（CLK1） PLL电路，分频比N1的第二分频器（32），通过以分频比N2分频由PLL电路产生的信号，产生频率为38kHz的第二时钟信号（CLK2）的第二分频器（32） 分频器（34），用于通过以分频比N3对由PLL电路产生的信号进行分频来产生具有48kHz频率的第三时钟信号（CLK3）。

公开(公告)号：US07561863B2

公开(公告)日：2009-07-14

申请号：US11441055

申请日：2006-05-26

申请人： Takeshi Ikeda ,  Hiroshi Miyagi

发明人： Takeshi Ikeda ,  Hiroshi Miyagi

IPC分类号： H04B1/06 ,  H04B7/00

CPC分类号： H03G3/3052

摘要： A received signal level is detected in each of a wide band, middle band, and narrow band and each detected signal is converted to a digital signal. A DSP 18 determines the enabled/disabled state of an LNA 3 and an attenuator 4 as well as a gain adjustment amount based on the signal level of each band. For example, the gain adjustment is not performed when the signal level of the narrow band including a desired frequency is not larger than a prescribed value even the signal level of the wide band or middle band is larger than a prescribed value. When the signal level of the narrow band is larger than the prescribed value exceeding a gain adjustable limit level in the attenuator 4, the gain of the LNA 3 is adjusted, while maintaining the gain adjustable amount in the attenuator 4 around the limit level, to reduce the gain as a whole.

摘要翻译： 在宽带，中频带和窄带中的每一个中检测到接收信号电平，并且将每个检测信号转换为数字信号。 DSP18根据每个频带的信号电平确定LNA 3和衰减器4的使能/禁止状态以及增益调整量。 例如，即使宽带或中频带的信号电平大于规定值，当包含期望频率的窄带的信号电平不大于规定值时，也不进行增益调整。 当窄带的信号电平大于衰减器4中超过增益可调极限电平的规定值时，调节LNA 3的增益，同时将衰减器4中的增益可调量保持在限制电平附近，至 减少整体收益。

公开(公告)号：US20090111416A1

公开(公告)日：2009-04-30

申请号：US12262470

申请日：2008-10-31

申请人： Kazuhisa Ishiguro

发明人： Kazuhisa Ishiguro

IPC分类号： H04B1/10

CPC分类号： H04B1/1018

摘要： There are provided a frequency converting circuit 21 for inputting a broadband IF signal which includes a disturbing wave and carrying out a frequency conversion with an oscillating signal having a frequency of a desirable wave, and outputting a signal including a sum frequency component of a frequency component of a disturbing wave which is included in the IF signal and a frequency component of a desirable wave of the oscillating signal and a difference frequency component therebetween, and a low-pass filter 22 for attenuating the sum frequency component to output a signal of the difference frequency component, and a presence of an intermodulation disturbance is detected based on a frequency relationship between two difference frequency components output from the low-pass filter 22. Consequently, it is possible to easily detect the intermodulation disturbance irrespective of a level of a received signal or a desirable wave included therein without carrying out a processing for amplitude modulating the received signal.

摘要翻译： 提供了一个频率转换电路21，用于输入包括干扰波的宽带IF信号，并用具有期望波频率的振荡信号进行频率转换，并输出包括频率分量的和频分量的信号 包括在IF信号中的干扰波和振荡信号的期望波的频率分量以及它们之间的差分频率分量的低通滤波器22以及用于衰减和频分量以输出差分信号的低通滤波器22 基于从低通滤波器22输出的两个差分分量之间的频率关系来检测频率分量和互调干扰的存在。因此，无论接收信号的电平如何，都可以容易地检测互调干扰 或其中包含的期望波，而不进行放大处理 去调制接收的信号。

公开(公告)号：US20090027128A1

公开(公告)日：2009-01-29

申请号：US12180063

申请日：2008-07-25

申请人： Kazuhisa Ishiguro

发明人： Kazuhisa Ishiguro

IPC分类号： H03G3/00

CPC分类号： H03G1/0088

摘要： The present invention provides a variable gain amplifier including a plurality of initial-stage LNAs 1 to 4 connected parallel to one input terminal IN, a next-stage LNA 5 connected after the initial-stage LNAs 1 to 4 and a variable current source 20 that performs control such that a total value of initial-stage control currents IB1 to IB4 simultaneously flowing through the initial-stage LNAs 1 to 4 is kept constant and such that-next-stage control currents IB13 and IB24 of magnitude proportional to the initial-stage control currents IB1 to IB4 which are let flow through the initial-stage LNAs 1 to 4 are let flow through the next-stage LNA 5, wherein the necessity for causing an excessively large fixed current to flow through the next-stage LNA 5 is eliminated and the next-stage control currents IB13 and IB24 are reduced to a minimum necessary magnitude so that increases of useless current consumption can be suppressed.

摘要翻译： 本发明提供一种可变增益放大器，包括与一个输入端子IN并联连接的多个初级LNA1〜4，在初级LNA1〜4之后连接的下一级LNA5和可变电流源20， 执行控制，使得同时流过初级LNA1至4的初级级控制电流IB1至IB4的总值保持恒定，使得下一级控制电流IB13和IB24与初始级成比例 使流过初级LNA1至4的控制电流IB1至IB4流过下一级LNA 5，其中消除了使过大的固定电流流过下一级LNA 5的必要性被消除 并且下一级控制电流IB13和IB24被减小到最小必需量，从而可以抑制无用电流消耗的增加。

公开(公告)号：US07403140B2

公开(公告)日：2008-07-22

申请号：US11751034

申请日：2007-05-20

申请人： Hiroshi Miyagi ,  Isami Kato

发明人： Hiroshi Miyagi ,  Isami Kato

IPC分类号： H03M1/06

CPC分类号： H04B1/28 ,  H03J1/005

摘要： An object of the present invention is to provide a receiver, a digital-analog converter and a tuning circuit in which temperature compensating components can be formed on a semiconductor substrate while reducing component costs. An FM receiver 100 is constituted by including an antenna 1, a high frequency receiving circuit 2, a local oscillator 3, two digital-analog converters (DACs) 4, 6, a control section 8, a mixing circuit 9, an intermediate frequency amplification circuit 10, a detection circuit 11, a low frequency amplification circuit 12 and the speaker 13. The DACs 4, 6 have a predetermined temperature coefficient, of which output voltage is changed in accordance with ambient temperature. When a characteristic of VCO 31 is changed with variations of ambient temperature so as to cause a control voltage applied to the VCO 31 to be changed, output voltages of the DACs 4, 6 are also changed similarly.

摘要翻译： 本发明的目的是提供一种接收器，数模转换器和调谐电路，其中可以在半导体衬底上形成温度补偿部件，同时降低部件成本。 FM接收机100包括天线1，高频接收电路2，本地振荡器3，两个数模转换器（DAC）4,6，控制部分8，混合电路9，中频放大 电路10，检测电路11，低频放大电路12和扬声器13。 DAC4,6具有预定的温度系数，其输出电压根据环境温度而改变。 当VCO 31的特性随着环境温度的变化而改变，以便施加到VCO 31的控制电压被改变时，DAC4,6的输出电压也被类似地改变。

公开(公告)号：US07378709B2

公开(公告)日：2008-05-27

申请号：US10484648

申请日：2002-06-28

申请人： Hiroshi Miyagi

发明人： Hiroshi Miyagi

IPC分类号： H01L29/00

CPC分类号： H01L27/0808 ,  H01L21/761 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243

摘要： An oscillator capable of reducing a noise component when partly formed by using the CMOS process or the MOS process. A high-frequency amplifier circuit, a mixing circuit, a local oscillator 13, intermediate-frequency filters, an intermediate-frequency amplifier circuit, a limit circuit, an FM detection circuit, and a stereo demodulation circuit which constitute an FM receiver are formed as a one-chip component. The local oscillator 13 is formed on a semiconductor substrate by using the CMOS process or the MOS process and the transistors constituting the circuit are p-channel type FETs 21, 22. Moreover, the local oscillator 13 has a resonance circuit whose one end is connected to a DC bias circuit composed of a resistor 27 and the center voltage of the oscillation is set to a value higher than 0 V.

摘要翻译： 能够通过使用CMOS工艺或MOS工艺部分地形成噪声分量的振荡器。 构成FM接收机的高频放大电路，混频电路，本地振荡器13，中频滤波器，中频放大器电路，限位电路，FM检测电路和立体声解调电路形成为 单芯片组件。 通过使用CMOS工艺或MOS工艺在半导体衬底上形成本地振荡器13，并且构成电路的晶体管是p沟道型FET 21,22。 此外，本地振荡器13具有谐振电路，其一端连接到由电阻器27组成的DC偏置电路，并且将振荡的中心电压设置为高于0V的值。