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公开(公告)号：US20240235565A1
公开(公告)日：2024-07-11
申请号：US18407613
申请日：2024-01-09
IPC分类号： H03M1/06
CPC分类号： H03M1/0604
摘要： A charge-injection SAR ADC device has a modified charge-injection cell (CIC), and a complementary to absolute temperature (CTAT) circuit for generating a bias voltage. The CIC and CTAT circuits cooperate to correct for process, voltage, and temperature (PVT) variation that affect SAR ADC input full scale. The CIC has been modified to have transistors that are in a cascoded relationship with transistors operating to maintain a reservoir of charge. The CTAT circuit is designed to substantially replicate the CIC, and it tracks the CIC operation to correct variations in transistor threshold voltage due to variations in PVT.
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公开(公告)号：US10938399B1
公开(公告)日：2021-03-02
申请号：US16893946
申请日：2020-06-05
申请人： Yuan-Ju Chao , Chia-Tung Lee
发明人： Yuan-Ju Chao , Chia-Tung Lee
IPC分类号： H03M1/06
摘要： A new SARADC has two low resolution SAR (Successive Approximation Register) ADCs coupled together by an amplifier to increase the overall resolution and enhance ADC conversion rate. The gain reduction of amplifier is corrected by shifting the digital binary output position. Two SAR ADC outputs are timing aligned and summed to produce final high-resolution high conversion rate ADC output.
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公开(公告)号：US20240235570A9
公开(公告)日：2024-07-11
申请号：US17971801
申请日：2022-10-24
申请人： YUAN-JU CHAO
发明人： YUAN-JU CHAO
IPC分类号： H03M1/12
CPC分类号： H03M1/1245
摘要： A method of eliminating reference voltage of Analog-to-Digital Converter to enhance faster conversion rate, achieve compact size and decrease power consumption for Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).
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公开(公告)号：US20220158651A1
公开(公告)日：2022-05-19
申请号：US16950950
申请日：2020-11-18
申请人： Yuan-Ju Chao
发明人： Yuan-Ju Chao
摘要： Computing-in-memory utilizes memory as weight for multiply-and-accumulate (MAC) operations. Input data multiplies weights to produce output data during the operation. Method of data conversion from input data, memory element to output data is described to enhance the computing efficiency.
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公开(公告)号：US20240137036A1
公开(公告)日：2024-04-25
申请号：US17971801
申请日：2022-10-23
申请人： YUAN-JU CHAO
发明人： YUAN-JU CHAO
IPC分类号： H03M1/12
CPC分类号： H03M1/1245
摘要： A method of eliminating reference voltage of Analog-to-Digital Converter to enhance faster conversion rate, achieve compact size and decrease power consumption for Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).
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公开(公告)号：US11652490B1
公开(公告)日：2023-05-16
申请号：US17521823
申请日：2021-11-08
申请人： Yuan-Ju Chao
发明人： Yuan-Ju Chao
CPC分类号： H03M1/0604 , H03M1/002 , H03M1/10 , H03M1/745 , H03M1/765
摘要： A method of expanding current steering Digital-to-Analog Converter (DAC) output amplitude and enhancing linearity performance. Level shifters with regulated supply and ground voltage are inserted before current source latches. Extra devices and small current are placed between switches and resistor load to enhance the linearity of current steering DAC.
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公开(公告)号：US20230148381A1
公开(公告)日：2023-05-11
申请号：US17521823
申请日：2021-11-08
申请人： YUAN-JU CHAO
发明人： YUAN-JU CHAO
IPC分类号： H03M1/06
CPC分类号： H03M1/0604
摘要： A method of expanding current steering Digital-to-Analog Converter (DAC) output amplitude and enhancing linearity performance. Level shifters with regulated supply and ground voltage are inserted before current source latches. Extra devices and small current are placed between switches and resistor load to enhance the linearity of current steering DAC.
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公开(公告)号：US11637561B2
公开(公告)日：2023-04-25
申请号：US16950950
申请日：2020-11-18
申请人： Yuan-Ju Chao
发明人： Yuan-Ju Chao
摘要： Computing-in-memory utilizes memory as weight for multiply-and-accumulate (MAC) operations. Input data multiplies weights to produce output data during the operation. Method of data conversion from input data, memory element to output data is described to enhance the computing efficiency.
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