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公开(公告)号：US20240272871A1
公开(公告)日：2024-08-15
申请号：US18107910
申请日：2023-02-09
Applicant: Arith Inc.
Inventor： David H.C. Chen
CPC classification number: G06F7/5525 , G06F7/49905 , G06F7/523
Abstract: Systems and methods are directed to accelerating operations associated with a microprocessor. Example embodiments improve the operations of the microprocessor by providing devices (e.g., integrated circuits, independent accelerators) configured to use reciprocal or reciprocal square root instructions. Such devices can be further configured to follow the reciprocal or reciprocal square root instructions with multiplication or other instructions to finish division, square root, or other complex operations.
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公开(公告)号：US10019228B2
公开(公告)日：2018-07-10
申请号：US14732814
申请日：2015-06-08
Applicant: International Business Machines Corporation
Inventor： Oliver Draese , Michael M. Skubowius , Knut Stolze
CPC classification number: G06F7/483 , G06F7/485 , G06F7/49905 , G06F7/5443
Abstract: A method for enhancing an accuracy of a sum of a plurality of floating-point numbers. The method receives a floating-point number and generates a plurality of provisional numbers with a value of zero. The method further generates a surjective map from the values of an exponent and a sign of a mantissa to the provisional numbers in the plurality of provisional numbers. The method further maps a value of the exponent and the sign of the mantissa to a first provisional number with the surjective map. The method further generates a test number from the first provisional number and if the test number exceeds a limit, modifies a second provisional number by using at least part of the test number. The method further equates the first provisional number to the test number if the test number does not exceed the limit. The method further sums the plurality of provisional numbers.
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公开(公告)号：US09785435B1
公开(公告)日：2017-10-10
申请号：US15335914
申请日：2016-10-27
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Jonathan D. Bradbury , Michael K. Gschwind , Silvia Melitta Mueller , Brett Olsson , Eric M. Schwarz
CPC classification number: G06F9/30021 , G06F7/483 , G06F7/49905 , G06F7/49926 , G06F7/49957 , G06F9/3001 , G06F9/30018 , G06F9/30025 , G06F9/30029 , G06F9/30036 , G06F9/30094 , G06F9/30109 , G06F9/30145 , G06F9/30174 , G06F9/30185 , G06F9/455
Abstract: An instruction to perform a comparison of a first value and a second value is executed. Based on a control of the instruction, a compare function to be performed is determined. The compare function is one of a plurality of compare functions configured for the instruction, and the compare function has a plurality of options for comparison. A compare option based on the first value and the second value is selected from the plurality of options defined for the compare function, and used to compare the first value and the second value. A result of the comparison is then placed in a select location, the result to be used in processing within a computing environment.
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公开(公告)号：US20160139882A1
公开(公告)日：2016-05-19
申请号：US14732814
申请日：2015-06-08
Applicant: International Business Machines Corporation
Inventor： Oliver Draese , Michael M. Skubowius , Knut Stolze
IPC: G06F7/485
CPC classification number: G06F7/483 , G06F7/485 , G06F7/49905 , G06F7/5443
Abstract: A method for enhancing an accuracy of a sum of a plurality of floating-point numbers. The method receives a floating-point number and generates a plurality of provisional numbers with a value of zero. The method further generates a surjective map from the values of an exponent and a sign of a mantissa to the provisional numbers in the plurality of provisional numbers. The method further maps a value of the exponent and the sign of the mantissa to a first provisional number with the surjective map. The method further generates a test number from the first provisional number and if the test number exceeds a limit, modifies a second provisional number by using at least part of the test number. The method further equates the first provisional number to the test number if the test number does not exceed the limit. The method further sums the plurality of provisional numbers.
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公开(公告)号：US20130173682A1
公开(公告)日：2013-07-04
申请号：US13339184
申请日：2011-12-28
Applicant: Marko Radmilac
Inventor： Marko Radmilac
IPC: G06F7/483
CPC classification number: G06F7/483 , G06F7/49905
Abstract: A process for propagating an error in a floating-point calculation is disclosed. A floating-point error occurring from the floating-point arithmetic calculation is trapped, and a special value is generated. Information regarding the error is stored as a payload of the special value. Program operations are resumed with the special value applied to further calculations dependent on the floating-point arithmetic calculation.
Abstract translation: 公开了一种在浮点计算中传播错误的过程。 从浮点运算计算出现的浮点错误被捕获，并产生一个特殊的值。 关于错误的信息被存储为特殊值的有效载荷。 程序操作恢复，特殊值应用于依赖于浮点运算的进一步计算。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20110296146A1
公开(公告)日：2011-12-01
申请号：US12788570
申请日：2010-05-27
Applicant: Christopher K. Anand , Robert F. Enenkel , Anuroop Sharma , Daniel M. Zabawa
Inventor： Christopher K. Anand , Robert F. Enenkel , Anuroop Sharma , Daniel M. Zabawa
IPC: G06F9/302
CPC classification number: G06F9/3001 , G06F7/483 , G06F7/49905 , G06F9/3893
Abstract: A set of instructions for implementation in a floating-point unit or other computer processor hardware is disclosed herein. In one embodiment, an extended-range fused multiply-add operation, a first look-up operation, and a second look-up operation are each embodied in hardware instructions configured to be operably executed in a processor. These operations are accompanied by a table which provides a set of defined values in response to various function types, supporting the computation of elementary functions such as reciprocal, square, cube, fourth roots and their reciprocals, exponential, and logarithmic functions. By allowing each of these functions to be computed with a hardware instruction, branching and predicated execution may be reduced or eliminated, while also permitting the use of distributed instructions across a number of execution units.
Abstract translation: 本文公开了一组用于在浮点单元或其他计算机处理器硬件中实现的指令。 在一个实施例中，扩展范围的融合乘法运算，第一查找操作和第二查找操作各自体现在被配置为在处理器中可操作地执行的硬件指令中。 这些操作伴随着一个表，其响应于各种功能类型提供一组定义的值，支持基本函数的计算，例如倒数，平方，立方，第四根及其倒数，指数函数和对数函数。 通过允许使用硬件指令来计算这些功能中的每一个，可以减少或消除分支和预测的执行，同时还允许在多个执行单元上使用分布式指令。
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公开(公告)号：US07366749B2
公开(公告)日：2008-04-29
申请号：US10035595
申请日：2001-12-28
Applicant: Guy L. Steele, Jr.
Inventor： Guy L. Steele, Jr.
IPC: G06F7/42
CPC classification number: G06F9/30094 , G06F5/012 , G06F5/015 , G06F7/483 , G06F7/485 , G06F7/4873 , G06F7/4876 , G06F7/49905 , G06F7/49942 , G06F9/30014 , G06F9/3861 , G06F9/3885 , G06F2207/3884
Abstract: A system for providing a floating point sum includes an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data with the second floating point operand respectively. In addition, the system includes a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the sum of the first floating point operand and the second floating point operand and a resulting status embedded within the resulting floating point operand.
Abstract translation: 一种用于提供浮点和的系统包括：分析器电路，被配置为基于第一浮点数操作数内的数据和具有第二浮点的数据确定第一浮点操作数的第一状态和第二浮点操作数的第二状态 操作数。 此外，该系统包括耦合到分析器电路的结果电路。 结果电路被配置为断言包含第一个浮点数操作数和第二个浮点操作数之和的结果浮点操作数，以及嵌入到生成的浮点操作数中的结果状态。
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8.发明授权公开(公告)号：US07236999B2
公开(公告)日：2007-06-26
申请号：US10320450
申请日：2002-12-17
Applicant: Guy L. Steele, Jr.
Inventor： Guy L. Steele, Jr.
CPC classification number: G06F7/49989 , G06F7/4873 , G06F7/49905
Abstract: Computing an output interval includes producing a first result from a conditional selection using a first operand, a second operand, and a third operand, the operands respectively including a second input interval upper-point, a first input interval upper-point, and a first input interval lower-point. Next, computing an output interval includes producing a second result from the conditional selection, the operands respectively including a second input interval upper-point, the first input interval upper-point, and the first input interval lower-point. Furthermore, computing an output interval includes producing a third result from a conditional division using the first operand, the second operand, and the third operand, the operands respectively including the first result, the second input interval upper-point, and the second input interval lower-point. And finally, a fourth result is produced from the conditional division, the operands respectively including the second result, the second input interval lower-point, and the second input interval upper-point.
Abstract translation: 计算输出间隔包括使用第一操作数，第二操作数和第三操作数从条件选择产生第一结果，所述操作数分别包括第二输入间隔上限点，第一输入间隔上限点和第一输入间隔上限值 输入间隔较低点。 接下来，计算输出间隔包括从条件选择产生第二结果，操作数分别包括第二输入间隔上限点，第一输入间隔上限点和第一输入间隔下限点。 此外，计算输出间隔包括使用第一操作数，第二操作数和第三操作数从条件划分产生第三结果，操作数分别包括第一结果，第二输入间隔上限点和第二输入间隔 低点 最后，从条件划分产生第四结果，操作数分别包括第二结果，第二输入间隔下位点和第二输入间隔上限。
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9.发明申请公开(公告)号：US20060242215A1
公开(公告)日：2006-10-26
申请号：US11394080
申请日：2006-03-31
Applicant: Guy Steele
Inventor： Guy Steele
IPC: G06F7/00
CPC classification number: G06F7/4876 , G06F5/012 , G06F5/015 , G06F7/44 , G06F7/483 , G06F7/4873 , G06F7/49905 , G06F7/544 , G06F9/30021 , G06F9/30094 , G06F9/3861 , G06F9/3885
Abstract: A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point status information encoded within the first floating point operand, a second analysis circuit configured to determine a format of a second floating point operand of the two floating point operands based upon floating point status information encoded within the second floating point operand, a decision circuit, coupled to the first analysis circuit and to the second analysis circuit and responding to a function control signal that indicates the threshold condition is one of a maximum of the two floating point operands and a minimum of the two floating point operands, for generating at least one assembly control signal based on the format of a first floating point operand, the format of a second floating point operand, and the function control signal, and a result assembler circuit, coupled to the decision circuit, for producing a result indicating which of the first floating point operand and the second floating point operand meet the threshold condition, based on the at least one assembly control signal. The format of the floating point operands may be from a group comprising: not-a-number (NaN), positive infinity, negative infinity, normalized, denormalized, positive overflow, negative overflow, positive underflow, negative underflow, inexact, exact, division by zero, invalid operation, positive zero, and negative zero. The result produced may be a third floating point operand having encoded floating point status information, and at least part of the encoded floating point status information in the result may come from either the first floating point operand or the second floating point operand.
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10.发明授权公开(公告)号：US07113969B1
公开(公告)日：2006-09-26
申请号：US10958185
申请日：2004-10-04
Applicant: Daniel W. Green , Atul Dhablania , Jeffrey A. Lohman
Inventor： Daniel W. Green , Atul Dhablania , Jeffrey A. Lohman
IPC: G06F7/38
CPC classification number: G06F7/49905 , G06F9/30025 , G06F9/30192
Abstract: A floating point unit (FPU) for processing denormal numbers in floating point notation, a method of processing such numbers in an FPU and a computer system employing the FPU or the method. In one embodiment, the FPU includes: (1) a load unit that receives a denormal number having an exponent portion of a standard length from a source without the FPU and transforms the denormal number into a normalized number having an exponent portion of an expanded length greater than the standard length, (2) a floating point execution core, coupled to the load unit, that processes the normalized number at least once to yield a processed normalized number, the expanded length of the exponent portion allowing the processed normalized number to remain normal during processing thereof and (3) a store unit, coupled to the floating point execution core, that receives the processed normalized number and transforms the processed normalized number back into a denormal number having an exponent portion of the standard length.
Abstract translation: 用于处理浮点符号中的异常数字的浮点单元（FPU），在FPU中处理这些数字的方法以及采用FPU或该方法的计算机系统。 在一个实施例中，FPU包括：（1）负载单元，其从没有FPU的源接收具有标准长度的指数部分的正规数，并将异常数转换为具有扩展长度的指数部分的归一化数 大于标准长度，（2）耦合到加载单元的浮点执行核，其处理归一化数至少一次以产生处理的归一化数，允许处理的归一化数保持的指数部分的扩展长度 并且（3）耦合到浮点执行核心的存储单元，其接收处理的归一化数，并将处理的归一化数转换回具有标准长度的指数部分的反正态数。
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