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57 条记录 (耗时 0.013 秒)

    Closed loop analog signal processor (“CLASP”) system
    3.
    发明授权
    Closed loop analog signal processor (“CLASP”) system 有权
    闭环模拟信号处理器（“CLASP”）系统

    公开(公告)号：US08630727B2

    公开(公告)日：2014-01-14

    申请号：US12757857

    申请日：2010-04-09

    申请人： Christopher A. Estes

    发明人： Christopher A. Estes

    IPC分类号： G06F17/00 ,  H04R1/40 ,  H04B1/00 ,  H04B1/20 ,  G11B17/00 ,  G11B20/10 ,  G11B27/22

    CPC分类号： G11B20/10527 ,  G11B5/027 ,  G11B20/02 ,  G11B20/1262 ,  H04H60/04

    摘要： A system, device, and method for recording audio with the character and sonic benefits of a genuine analog recording is disclosed. More specifically, an electro-mechanical-software controlled closed loop analog signal processor (“CLASP”) system which is comprised of a CLASP unit containing firmware, a latency detection module, and CLASP hardware display and controls. The CLASP system further comprises CLASP software operably running on a digital audio workstation (“DAW”) which is also in operable communication with the CLASP unit. The CLASP unit is also in operable communication with an analog recordable medium. An analog audio signal is recorded on the analog recordable medium, which may consist of a coated tape, cup, cylinder, drum, or disk, and then immediately played back and routed to the DAW via an analog to digital converter, thus providing for digitally recorded analog audio. The CLASP system may also include converters and a mixing console.

    摘要翻译： 公开了一种用于记录具有真实模拟记录的特征和声音优点的音频的系统，设备和方法。 更具体地说，一种由包含固件的CLASP单元，等待时间检测模块和CLASP硬件显示和控制组成的机电软件控制的闭环模拟信号处理器（“CLASP”）系统。 CLASP系统还包括可操作地在数字音频工作站（“DAW”）上运行的CLASP软件，其也可与CLASP单元可操作地通信。 CLASP单元还可与可模拟可记录介质进行可操作的通信。 模拟音频信号被记录在模拟可记录媒体上，可以由涂覆的胶带，杯，圆筒，鼓或磁盘组成，然后立即通过模数转换器回放并路由到DAW，从而提供数字化 记录模拟音频。 CLASP系统还可以包括转换器和调音台。

    Signal translating circuit
    4.
    发明授权
    Signal translating circuit 失效
    信号转换电路

    公开(公告)号：US4559501A

    公开(公告)日：1985-12-17

    申请号：US564099

    申请日：1983-12-22

    申请人： Tooru Akutagawa ,  Yukihiko Machida

    发明人： Tooru Akutagawa ,  Yukihiko Machida

    IPC分类号： H03F3/34 ,  G11B5/027 ,  G11B5/03 ,  H03F1/34 ,  H03F3/04

    CPC分类号： G11B5/03 ,  G11B5/027

    摘要： A signal translating circuit comprises first and second transistors connected to each other in such a manner that a collector of the first transistor is coupled with a base of the second transistor and an emitter of the second transistor is coupled with a base of the first transistor so as to form a negative feedback circuit arrangement, an input resistor connected between the base of the first transistor and a source of an input voltage signal for converting the input voltage signal into an input current signal to be supplied to the base of the first transistor, a biasing current source connected to the base of the first transistor, first and second current sources supplying the same currents and connected to the emitter of the first transistor and a collector of the second transistor, respectively, and means for deriving an output current signal from the collector of the second transistor.

    摘要翻译： 信号转换电路包括彼此连接的第一和第二晶体管，使得第一晶体管的集电极与第二晶体管的基极耦合，并且第二晶体管的发射极与第一晶体管的基极耦合， 为了形成负反馈电路装置，连接在第一晶体管的基极和输入电压信号的源之间的输入电阻器，用于将输入电压信号转换为要提供给第一晶体管的基极的输入电流信号， 连接到第一晶体管的基极的偏置电流源，分别提供相同电流并连接到第一晶体管的发射极和第二晶体管的集电极的第一和第二电流源，以及用于从第一晶体管的基极导出输出电流信号的装置， 第二晶体管的集电极。

    Suppressing pulse synthesizer
    5.
    发明授权
    Suppressing pulse synthesizer 失效
    抑制脉冲合成器

    公开(公告)号：US4197507A

    公开(公告)日：1980-04-08

    申请号：US894462

    申请日：1978-04-07

    申请人： Robert E. Cunningham ,  Philip H. Bush

    发明人： Robert E. Cunningham ,  Philip H. Bush

    IPC分类号： G11B5/027 ,  H03K5/13 ,  H03K5/153 ,  H03K5/18 ,  H03K13/32

    CPC分类号： G11B5/027

    摘要： A supressing pulse synthesizer for supplying the proper average number of nchronization pulses from a reproduced reference signal to an analog to digital converter utilized to convert analog data present on a magnetic tape to digital data.

    摘要翻译： 一种抑制脉冲合成器，用于从再现的参考信号向用于将存在于磁带上的模拟数据转换为数字数据的模数转换器提供适当的平均数量的同步脉冲。

    Amplifier system
    6.
    发明授权
    Amplifier system 失效
    放大器系统

    公开(公告)号：US3825847A

    公开(公告)日：1974-07-23

    申请号：US31471872

    申请日：1972-12-13

    申请人： LORRAINE IND INC

    发明人： HUGHES D ,  SHERWOOD H

    IPC分类号： G11B5/027 ,  H03F3/18 ,  H03F3/30

    CPC分类号： H03F3/3071 ,  G11B5/027

    摘要： A cassette recorder amplifier system with a two stage preamplifier having direct current forward feed from the first to the second stage and direct current feedback from the second to the first stage to cause the second stage to operate without overloading as an input stage. The power amplifier has high direct current feedback and lower alternating current feedback for better linearity and more gain. Switch circuits and extra input terminals provide for recording on recording, aural monitoring of recording, and higher speed on fast forward and reverse.

    摘要翻译： 具有两级前置放大器的盒式录放放大器系统具有从第一级到第二级的直接电流正向馈送，以及从第二级到第一级的直流电反馈，以使第二级在不过载作为输入级的情况下运行。 功率放大器具有较高的直流电流反馈和较低的交流电流反馈，从而获得更好的线性度和更多的增益。 开关电路和额外的输入端子用于记录录音，录音监听，快进和快退。

    Magnetic tape recording circuit
    7.
    发明授权
    Magnetic tape recording circuit 失效
    磁带录音电路

    公开(公告)号：US3683131A

    公开(公告)日：1972-08-08

    申请号：US3683131D

    申请日：1965-06-28

    申请人： BELL & HOWELL CO

    发明人： HODDER WAYNE K ,  BROWDER LEWIS B

    IPC分类号： G11B5/027 ,  H03F1/56 ,  H03F3/183 ,  G11B5/44

    CPC分类号： H03F1/56 ,  G11B5/027 ,  H03F3/183

    摘要： There is described a recording amplifier circuit for a magnetic recorder providing a very low output impedance in series with the winding on the magnetic recording head. The low output impedance is achieved by negative feedback, preferably derived from the voltage across the drive coil or derived from a separate coil on the magnetic head wound concentrically with the drive coil.

    摘要翻译： 描述了一种用于磁记录器的记录放大器电路，其提供与磁记录头上的绕组串联的非常低的输出阻抗。 低输出阻抗通过负反馈来实现，优选地源于驱动线圈两端的电压，或者源自与驱动线圈同心缠绕在磁头上的单独线圈。

    Preamplifier with Read/Write Power Channels
    10.
    发明公开
    Preamplifier with Read/Write Power Channels 审中-公开

    公开(公告)号：US20230197108A1

    公开(公告)日：2023-06-22

    申请号：US17557528

    申请日：2021-12-21

    申请人： Western Digital Technologies, Inc.

    发明人： Joey M. Poss ,  Erhard Schreck

    IPC分类号： G11B5/027

    CPC分类号： G11B5/027

    摘要： Example preamplifier circuits, data storage devices, and methods to provide a preamplifier circuit with separate read and write power channels are described. The preamplifier circuit may include a write driver circuit configured to send a write signal to a writer element of a data storage device and a read driver circuit configured to receive a read signal from a reader element of the data storage device. The write driver circuit may receive a write power signal through a write power channel of a bus interface and the read driver circuit may receive a read power signal through a read power channel of the bus interface, where the write power signal and the read power signal are different. In some configurations, the different read and write power signals may be received from a switching regulator on the printed circuit board that mounts other data storage device electronics, such as the drive controller circuit and/or read/write channel circuit.