Signal processing device and image display apparatus including the same

    公开(公告)号:US11594202B2

    公开(公告)日:2023-02-28

    申请号:US17238779

    申请日:2021-04-23

    发明人: Jihoon Lee

    IPC分类号: G09G5/395 G09G3/20

    摘要: The present disclosure relates to a signal processing device and an image display apparatus including the same. The signal processing device includes a synchronizer configured to perform Fourier transform based on the received baseband signal, and an equalizer configured to extract a pilot signal from a signal from the synchronizer, to calculate a channel transfer function value of the extracted pilot signal, and to selectively perform time interpolation based on the calculated channel transfer function value. Thus, time interpolation is selectively performed based on the channel.

    IMAGE OUTPUT DEVICE AND IMAGE OUTPUT METHOD

    公开(公告)号:US20220165237A1

    公开(公告)日:2022-05-26

    申请号:US17525981

    申请日:2021-11-15

    IPC分类号: G09G5/395 G09G5/393

    摘要: The invention provides an image output device coupled to a first and second signal source and a method thereof. The image output device includes memories configured to store frame image data respectively, a source selection circuit coupled to the first and second signal sources and the memories and configured to choose to store a first frame image data transmitted by the first or second signal source in one of the memories according to a working state of the first signal source, and an image output circuit coupled to the memories and the source selection circuit and configured to output the first frame image data stored in one of the memories. The image output device may rapidly switch to a backup signal source when the signal source is unstable to achieve fast switching and perfect connection.

    INDIRECT CHAINING OF COMMAND BUFFERS

    公开(公告)号:US20220058767A1

    公开(公告)日:2022-02-24

    申请号:US17519992

    申请日:2021-11-05

    摘要: Systems, apparatuses, and methods for enabling indirect chaining of command buffers are disclosed. A system includes at least first and second processors and a memory. The first processor generates a plurality of command buffers and stores the plurality of command buffers in the memory. The first processor also generates and stores, in the memory, a table with entries specifying addresses of the plurality of command buffers and an order in which to process the command buffers. The first processor conveys an indirect buffer packet to the second processor, where the indirect buffer packet specifies a location and a size of the table in the memory. The second processor retrieves an initial entry from the table, processes a first command buffer at the address specified in the initial entry, and then returns to the table for the next entry upon completing processing of the first command buffer.

    Timestamp based display update mechanism

    公开(公告)号:US11211036B2

    公开(公告)日:2021-12-28

    申请号:US16919495

    申请日:2020-07-02

    申请人: Apple Inc.

    摘要: Systems, apparatuses, and methods for implementing a timestamp based display update mechanism. A display control unit includes a timestamp queue for storing timestamps, wherein each timestamp indicates when a corresponding frame configuration set should be fetched from memory. At pre-defined intervals, the display control unit may compare the timestamp of the topmost entry of the timestamp queue to a global timer value. If the timestamp is earlier than the global timer value, the display control unit may pop the timestamp entry and fetch the frame next configuration set from memory. The display control unit may then apply the updates of the frame configuration set to its pixel processing elements. After applying the updates, the display control unit may fetch and process the source pixel data and then drive the pixels of the next frame to the display.