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    SYSTEMS AND METHODS TO DISSIPATE HEAT IN AN INFORMATION HANDLING SYSTEM
    95.
    发明申请
    SYSTEMS AND METHODS TO DISSIPATE HEAT IN AN INFORMATION HANDLING SYSTEM 有权
    在信息处理系统中散热的系统和方法

    公开(公告)号：US20100155047A1

    公开(公告)日：2010-06-24

    申请号：US12338006

    申请日：2008-12-18

    Applicant: Chung-Hsiung Lin ,  Chien-Ting Lin

    Inventor： Chung-Hsiung Lin ,  Chien-Ting Lin

    IPC: G05D23/00 ,  F28F27/00

    CPC classification number: H05K7/207 ,  G05D23/1932 ,  G06F1/206 ,  G06F2200/201 ,  H01L23/34 ,  H01L23/467 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a particular embodiment, a system to dissipate heat in an information handling system includes a first heat-generating component adapted to process first data and a second heat-generating component adapted to process second data. The system also includes a cooling fluid guide including an electroactive material. The cooling fluid guide is adapted to change from a first shape to a second shape, in response to receiving a trigger voltage or in response to no longer receiving the trigger voltage. The system also includes a controller adapted to detect a data load processed at the second heat-generating component and, in response to detecting the data load, to cause the trigger voltage to be received at, or no longer received at, the cooling fluid guide. The cooling fluid guide is adapted to direct an increased portion of cooling fluid toward the first heat-generating component when the cooling fluid guide is in a form of the second shape, as compared to the first shape.

    Abstract translation: 在特定实施例中，在信息处理系统中散热的系统包括适于处理第一数据的第一发热组件和适于处理第二数据的第二发热组件。 该系统还包括包括电活性材料的冷却流体引导件。 响应于接收到触发电压或响应于不再接收到触发电压，冷却流体引导件适于从第一形状变化到第二形状。 该系统还包括控制器，适于检测在第二发热部件处理的数据负载，并且响应于检测到数据负载，使得触发电压在冷却流体导向件处接收或不再接收 。 与第一形状相比，当冷却流体引导件处于第二形状的形式时，冷却流体引导件适于将增加的冷却流体部分引向第一发热部件。

    METHOD FOR FABRICATING A METAL GATE STRUCTURE
    97.
    发明申请
    METHOD FOR FABRICATING A METAL GATE STRUCTURE 有权
    制作金属结构结构的方法

    公开(公告)号：US20090258482A1

    公开(公告)日：2009-10-15

    申请号：US12101160

    申请日：2008-04-11

    Applicant: Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

    Inventor： Chien-Ting Lin ,  Che-Hua Hsu ,  Li-Wei Cheng

    IPC: H01L21/283

    CPC classification number: H01L21/28123 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    Abstract: A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process.

    Abstract translation: 提供一种制造金属栅极结构的方法。 该方法包括：提供具有平坦化多晶硅材料的半导体衬底; 将平坦化的多晶硅材料图案化以形成至少第一栅极和第二栅极，其中第一栅极位于有源区上，而第二栅极至少部分地与隔离区重叠; 形成覆盖所述栅极的层间电介质材料; 平面化层间电介质材料，直到露出栅极并形成层间介电层; 执行蚀刻工艺以移除所述栅极以在所述层间电介质层内形成第一凹部和第二凹槽; 在每个所述凹部的表面上形成栅极电介质材料; 在所述凹部内形成至少一种金属材料; 并执行平面化处理。

    Semiconductor CMOS transistors and method of manufacturing the same
    99.
    发明授权
    Semiconductor CMOS transistors and method of manufacturing the same 有权
    半导体CMOS晶体管及其制造方法相同

    公开(公告)号：US07589385B2

    公开(公告)日：2009-09-15

    申请号：US11161170

    申请日：2005-07-26

    Applicant: Chien-Ting Lin ,  Liang-Wei Chen ,  Che-Hua Hsu ,  Meng-Lin Lee ,  Hui-Chen Chang ,  Wei-Tsun Shiau

    Inventor： Chien-Ting Lin ,  Liang-Wei Chen ,  Che-Hua Hsu ,  Meng-Lin Lee ,  Hui-Chen Chang ,  Wei-Tsun Shiau

    IPC: H01L27/92

    CPC classification number: H01L21/823864 ,  H01L21/823807 ,  H01L29/7843

    Abstract: A CMOS transistor device including a tensile-stressed NMOS transistor and a PMOS transistor is disclosed. The NMOS transistor includes a gate, a gate oxide layer between the gate and semiconductor substrate, a silicon oxide offset spacer on sidewalls of the gate, N type lightly doped source/drain implanted into the semiconductor substrate next to the silicon oxide offset spacer, N type heavily doped source/drain implanted into the semiconductor substrate next to the N type lightly doped source/drain, and tensile-stressed silicon nitride layer covering the gate, the N type lightly doped source/drain, and the N type heavily doped source/drain.

    Abstract translation: 公开了一种包括拉伸应力NMOS晶体管和PMOS晶体管的CMOS晶体管器件。 NMOS晶体管包括栅极，栅极和半导体衬底之间的栅极氧化物层，栅极侧壁上的氧化硅偏移间隔物，注入到氧化硅偏移间隔物旁边的半导体衬底中的N型轻掺杂源/漏极，N 在N型轻掺杂源极/漏极旁边注入到半导体衬底中的重掺杂源极/漏极，覆盖栅极的拉伸应力氮化硅层，N型轻掺杂源极/漏极和N型重掺杂源极/ 排水。

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