中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

262 records (took 0.021 seconds)

    Strain-inducing semiconductor regions
    91.
    发明授权
    Strain-inducing semiconductor regions 有权
    应变诱导半导体区域

    公开(公告)号：US07629603B2

    公开(公告)日：2009-12-08

    申请号：US11450744

    申请日：2006-06-09

    Applicant: Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

    Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

    IPC: H01L31/00

    CPC classification number: H01L29/1054 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

    Abstract: A method to form a strain-inducing semiconductor region comprising three or more species of charge-neutral lattice-forming atoms is described. In one embodiment, formation of a strain-inducing semiconductor region, comprising three or more species of charge-neutral lattice-forming atoms, laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate. Thus, a strained crystalline substrate may be provided. In another embodiment, a semiconductor region with a crystalline lattice of three or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate.

    Abstract translation: 描述了形成包含三种或更多种电荷 - 中性晶格形成原子的应变诱导半导体区域的方法。 在一个实施方案中，形成包含三个或更多种电荷 - 中性晶格形成原子的应变诱导半导体区域，横向邻近晶体衬底导致赋予晶体衬底的单轴应变。 因此，可以提供应变晶体衬底。 在另一个实施方案中，具有三种或更多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底施加应变，其中半导体区域的晶格常数不同于晶体衬底的晶格常数。

    MULTI-GATE DEVICE HAVING A T-SHAPED GATE STRUCTURE
    92.
    发明申请
    MULTI-GATE DEVICE HAVING A T-SHAPED GATE STRUCTURE 有权
    具有T形门结构的多门装置

    公开(公告)号：US20090206406A1

    公开(公告)日：2009-08-20

    申请号：US12032603

    申请日：2008-02-15

    Applicant: Willy Rachmady ,  Uday Shah ,  Jack T. Kavalieros

    Inventor： Willy Rachmady ,  Uday Shah ,  Jack T. Kavalieros

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/42376 ,  H01L21/28114 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: A multi-gate device having a T-shaped gate structure is generally described. In one example, an apparatus includes a semiconductor substrate, at least one multi-gate fin coupled with the semiconductor substrate, the multi-gate fin having a gate region, a source region, and a drain region, the gate region being positioned between the source and drain regions, a gate dielectric coupled to the gate region of the multi-gate fin, a gate electrode coupled to the gate dielectric, the gate electrode having a first thickness and a second thickness, the second thickness being greater than the first thickness, a first spacer dielectric coupled to a portion of the gate electrode having the first thickness, and a second spacer dielectric coupled to the first spacer dielectric and coupled to the gate electrode where the second spacer dielectric is coupled to a portion of the gate electrode having the second thickness.

    Abstract translation: 通常描述具有T形门结构的多栅极器件。 在一个示例中，设备包括半导体衬底，与半导体衬底耦合的至少一个多栅极鳍，多栅极鳍具有栅极区，源极区和漏极区，栅极区位于 源极和漏极区域，耦合到多栅极鳍的栅极区域的栅极电介质，耦合到栅极电介质的栅电极，栅电极具有第一厚度和第二厚度，第二厚度大于第一厚度 耦合到具有第一厚度的栅电极的一部分的第一间隔电介质和耦合到第一间隔电介质并耦合到栅电极的第二间隔电介质，其中第二间隔电介质耦合到栅电极的一部分， 第二厚度。

    Fabrication of germanium nanowire transistors
    93.
    发明申请
    Fabrication of germanium nanowire transistors 有权
    锗纳米线晶体管的制造

    公开(公告)号：US20090170251A1

    公开(公告)日：2009-07-02

    申请号：US12006273

    申请日：2007-12-31

    Applicant: Been-Yih Jin ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Marko Radosavlievic ,  Robert S. Chau

    Inventor： Been-Yih Jin ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Marko Radosavlievic ,  Robert S. Chau

    IPC: H01L21/8234

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/78684 ,  H01L29/78696

    Abstract: In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.

    Abstract translation: 通常，在一个方面，一种方法包括使用锗纳米线作为高性能逻辑，存储器和低维量子效应器件的构建块。 锗纳米线通道和SiGe锚定区域通过外延硅锗外延层的优先Si氧化同时形成。 使用Si翅片作为模板来实现锗纳米线的放置，并且锗纳米线通过掩蔽翅片的两端而形成的SiGe锚定件保持在Si衬底上。 高介电常数栅极氧化物和功函数金属缠绕在锗纳米线上，用于门极全静电通道开/关控制，而锗纳米线在晶体管沟道区域提供高载流子迁移率。 锗纳米线晶体管可实现逻辑和存储器件的高性能，低电压（低功耗）操作。

    REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE BY INCORPORATION OF A PARTIAL METALLIC FIN
    94.
    发明申请
    REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE BY INCORPORATION OF A PARTIAL METALLIC FIN 有权
    通过加入部分金属粉末来降低多门装置的外部电阻

    公开(公告)号：US20090166742A1

    公开(公告)日：2009-07-02

    申请号：US11964623

    申请日：2007-12-26

    Applicant: Ravi Pillarisetty ,  Uday Shah ,  Titash Rakshit ,  Jack T. Kavalieros ,  Brian S. Doyle

    Inventor： Ravi Pillarisetty ,  Uday Shah ,  Titash Rakshit ,  Jack T. Kavalieros ,  Brian S. Doyle

    IPC: H01L29/94 ,  H01L21/8234

    CPC classification number: H01L29/785 ,  H01L29/66795

    Abstract: Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.

    Abstract translation: 通常描述通过结合部分金属翅片来降低多栅极器件的外部电阻。 在一个示例中，设备包括半导体衬底和与半导体衬底耦合的多栅极晶体管器件的一个或多个鳍片，该一个或多个鳍片具有栅极区域，源极区域和漏极区域，栅极区域 设置在源极和漏极区域之间，其中一个或多个鳍片的栅极区域包括半导体材料，并且其中一个或多个鳍片的源极和漏极区域包括金属部分和半导体部分，金属部分和半导体 部分联接在一起。

    REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES
    95.
    发明申请
    REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES 有权
    使用间隔加工技术降低多门装置的外部电阻

    公开(公告)号：US20090166741A1

    公开(公告)日：2009-07-02

    申请号：US11964593

    申请日：2007-12-26

    Applicant: Ravi Pillarisetty ,  Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros

    Inventor： Ravi Pillarisetty ,  Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros

    IPC: H01L29/94 ,  H01L21/336

    CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/785

    Abstract: Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.

    Abstract translation: 通常描述使用间隔物处理技术降低多栅极器件的外部电阻。 在一个示例中，一种方法包括将牺牲栅电极沉积到一个或多个多栅极散热片上，一个或多个多栅极鳍片包括栅极区域，源极区域和漏极区域，栅极区域设置在 源极和漏极区域，图案化牺牲栅极电极，使得牺牲栅电极材料耦合到栅极区域，并且基本上没有牺牲栅极电极耦合到一个或多个多栅极鳍片的源极和漏极区域，形成电介质 薄膜耦合到一个或多个多栅极鳍片的源极和漏极区域，从一个或多个多栅极鳍片的栅极区域去除牺牲栅电极，将间隔栅极电介质沉积到该一个或多个多栅极散热片的栅极区域 多栅极翅片，其中基本上没有间隔栅极电介质沉积到一个或多个多栅极鳍片的源极和漏极区域，源极和漏极区域被电介质fi 并且蚀刻间隔栅极电介质，以将栅极区域的栅极区域完全去除以与最终栅电极耦合的间隔栅极电介质，除了要与保持耦合的最终栅电极耦合的间隔栅极电介质的剩余预定厚度 与电介质膜。

    FABRICATING DUAL LAYER GATE ELECTRODES HAVING POLYSILICON AND A WORKFUNCTION METAL
    97.
    发明申请
    FABRICATING DUAL LAYER GATE ELECTRODES HAVING POLYSILICON AND A WORKFUNCTION METAL 审中-公开
    制造具有多晶硅和工作金属的双层门电极

    公开(公告)号：US20090061611A1

    公开(公告)日：2009-03-05

    申请号：US11848239

    申请日：2007-08-30

    Applicant: Willy Rachmady ,  Uday Shah ,  Jack T. Kavalieros ,  Brian S. Doyle

    Inventor： Willy Rachmady ,  Uday Shah ,  Jack T. Kavalieros ,  Brian S. Doyle

    IPC: H01L21/3205

    CPC classification number: H01L29/4958 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/66795 ,  H01L29/785

    Abstract: A method for fabricating a dual layer gate electrode having a polysilicon layer and a workfunction metal layer comprises depositing a layer of a workfunction metal on a semiconductor substrate, depositing a layer of polysilicon on the workfunction metal layer, depositing a hard mask layer on the polysilicon layer, etching the hard mask layer to form a hard mask structure defining a gate electrode, etching the polysilicon layer to remove a portion of the polysilicon layer not protected by the hard mask structure, thereby forming a polysilicon structure beneath the hard mask structure, applying a mixture of ozone and water to exposed sidewalls of the polysilicon structure, thereby forming a silicon dioxide layer on the sidewalls, and etching the workfunction metal layer to remove a portion of the workfunction metal layer not protected by the hard mask structure, thereby forming a workfunction metal structure beneath the polysilicon structure.

    Abstract translation: 一种用于制造具有多晶硅层和功函数金属层的双层栅电极的方法，包括在半导体衬底上沉积功函数金属层，在功函数金属层上沉积多晶硅层，在多晶硅上沉积硬掩模层 蚀刻硬掩模层以形成限定栅电极的硬掩模结构，蚀刻多晶硅层以去除未被硬掩模结构保护的多晶硅层的一部分，从而在硬掩模结构下方形成多晶硅结构，施加 将臭氧和水的混合物混合到多晶硅结构的暴露的侧壁，从而在侧壁上形成二氧化硅层，并蚀刻功函数金属层以除去未被硬掩模结构保护的功能金属层的一部分，从而形成 多晶硅结构下面的功函数金属结构。

Patent Agency Ranking