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1.Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions 有权
标题翻译: 隧道场效应晶体管使用成角度的植入物形成不对称的源极/漏极区域公开(公告)号:US07465976B2
公开(公告)日:2008-12-16
申请号:US11129520
申请日:2005-05-13
申请人: Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Ben Jin , Justin K. Brask , Suman Datta , Robert S. Chau
发明人: Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Ben Jin , Justin K. Brask , Suman Datta , Robert S. Chau
IPC分类号: H01L29/76
CPC分类号: H01L29/7391
摘要: The present invention relates to a Tunnel Field Effect Transistor (TFET). which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The IFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.
摘要翻译: 隧道场效应晶体管技术领域本发明涉及隧道场效应晶体管(TFET)。 其利用角度注入和非晶化形成不对称的源极和漏极区域。 IFET还包括具有与漏极相反的导电性的硅锗合金外延源区。
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2.Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions 有权
标题翻译: 隧道场效应晶体管使用成角度的植入物形成不对称的源极/漏极区域公开(公告)号:US20080318385A1
公开(公告)日:2008-12-25
申请号:US12229459
申请日:2008-08-22
申请人: Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau
发明人: Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau
IPC分类号: H01L21/336
CPC分类号: H01L29/7391
摘要: The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further comprises a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.
摘要翻译: 隧道场效应晶体管技术领域本发明涉及一种隧道场效应晶体管(TFET),其利用角度注入和非晶化形成不对称的源极和漏极区域。 TFET还包括具有与漏极相反的导电性的硅锗合金外延源区域。
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3.Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions 有权
标题翻译: 隧道场效应晶体管使用成角度的植入物形成不对称的源极/漏极区域公开(公告)号:US07888221B2
公开(公告)日:2011-02-15
申请号:US12229459
申请日:2008-08-22
申请人: Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau
发明人: Jack T. Kavalieros , Matthew V. Metz , Gilbert Dewey , Been-Yih Jin , Justin K. Brask , Suman Datta , Robert S. Chau
IPC分类号: H01L21/336
CPC分类号: H01L29/7391
摘要: The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further includes a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.
摘要翻译: 隧道场效应晶体管技术领域本发明涉及一种隧道场效应晶体管(TFET),其利用角度注入和非晶化形成不对称的源极和漏极区域。 TFET还包括具有与漏极相反的导电性的硅锗合金外延源区。
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公开(公告)号:US07989280B2
公开(公告)日:2011-08-02
申请号:US12338839
申请日:2008-12-18
申请人: Justin K. Brask , Suman Datta , Mark L. Doczy , James M. Blackwell , Matthew V. Metz , Jack T. Kavalieros , Robert S. Chau
发明人: Justin K. Brask , Suman Datta , Mark L. Doczy , James M. Blackwell , Matthew V. Metz , Jack T. Kavalieros , Robert S. Chau
IPC分类号: H01L21/336
CPC分类号: H01L21/314 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28008 , H01L21/3141 , H01L21/31616 , H01L21/31645 , H01L29/2003 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/66462 , H01L29/7784
摘要: A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.
摘要翻译: 描述了III-V族半导体器件及其制造方法。 高k电介质通过硫族化物区域连接到约束区域。
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5.PROCESS FOR INTEGRATING PLANAR AND NON-PLANAR CMOS TRANSISTORS ON A BULK SUBSTRATE AND ARTICLE MADE THEREBY 有权
标题翻译: 在大容量基板上集成平面和非平面CMOS晶体管的过程及其制造公开(公告)号:US20090090976A1
公开(公告)日:2009-04-09
申请号:US12333248
申请日:2008-12-11
申请人: Jack T. Kavalieros , Justin K. Brask , Brian S. Doyle , Uday Shah , Suman Datta , Mark L. Doczy , Matthew V. Metz , Robert S. Chau
发明人: Jack T. Kavalieros , Justin K. Brask , Brian S. Doyle , Uday Shah , Suman Datta , Mark L. Doczy , Matthew V. Metz , Robert S. Chau
IPC分类号: H01L29/78
CPC分类号: H01L21/823828 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L29/1037 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
摘要翻译: 一种能够将平面和非平面晶体管集成到体半导体衬底上的工艺,其中所有晶体管的沟道可在连续的宽度范围内定义。
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公开(公告)号:US20140291615A1
公开(公告)日:2014-10-02
申请号:US14302371
申请日:2014-06-11
申请人: Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人: Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号: H01L27/092 , H01L29/15
CPC分类号: H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译: CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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公开(公告)号:US20120199813A1
公开(公告)日:2012-08-09
申请号:US13450359
申请日:2012-04-18
申请人: Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人: Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号: H01L27/092 , H01L21/8238
CPC分类号: H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译: CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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公开(公告)号:US08802517B2
公开(公告)日:2014-08-12
申请号:US13962890
申请日:2013-08-08
申请人: Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人: Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号: H01L21/338
CPC分类号: H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译: CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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公开(公告)号:US20130328015A1
公开(公告)日:2013-12-12
申请号:US13962890
申请日:2013-08-08
申请人: Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人: Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号: H01L27/092 , H01L21/8238
CPC分类号: H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译: CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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公开(公告)号:US07858481B2
公开(公告)日:2010-12-28
申请号:US11154138
申请日:2005-06-15
申请人: Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
发明人: Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
IPC分类号: H01L21/336
CPC分类号: H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/4236 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/66818 , H01L29/7834 , H01L29/7838 , H01L29/785 , H04B1/3827 , Y10S438/926
摘要: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
摘要翻译: 描述了制造具有减薄沟道区的MOS晶体管的方法。 在去除虚拟栅极之后蚀刻沟道区。 源极和漏极区域具有相对较低的电阻。
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