Abstract:
A liquid crystal display screen includes an upper component, a bottom component and a liquid crystal layer. The upper component includes a touch panel. The touch panel includes a first conductive layer. The first conductive layer includes a transparent carbon nanotube structure. The bottom component includes a thin film transistor panel. The thin film transistor panel includes a plurality of thin film transistors. Each of the plurality of thin film transistors includes a semiconducting layer, and the semiconducting layer includes a semiconducting carbon nanotube structure. The liquid crystal layer is located between the upper component and the lower component.
Abstract:
A soldering system includes a circuit board having first soldering terminals, a soldering object having second soldering terminals, soldering blocks disposed between the circuit board and the soldering object for electrically interconnecting the first soldering terminals and the second soldering terminals respectively, and a supporting structure supporting the soldering object and having a height that determines the height of the solder blocks. A related soldering method is also provided.
Abstract:
An exemplary diffuser plate includes a diffuser film. The diffuser film includes a plurality of diffusion particles distributed therein. A refractive index of the outer shell of each diffusion particle exceeds that of the inner surface of each diffusion particle.
Abstract:
The video data output from the dot-inversion driver is re-arranged in the present invention. According this re-arranged method, the video data output from the even data lines or odd data lines is delayed for one scan line scan time. Then, the re-arranged video data are applied to the liquid crystal display structure whose thin film transistors connected with the same scan line are arranged in alternatingly up-down form to store row-inversion driving data in the pixel region.
Abstract:
An exemplary liquid crystal display device (300) includes a TFT substrate (311) and a color filter substrate (312) opposite to the TFT substrate; a space (313) defined between the TFT and the color filter substrates; and a liquid crystal layer (314) and a plurality of bumps (315, 316) located in the space. The bumps respectively extend from inner surfaces of the TFT and the color filter substrates. The bumps extending from the TFT substrate are arranged in first horizontal rows, and the bumps extending from the color filter substrate are arranged in second horizontal rows. Each of the first rows of bumps is slightly above a corresponding second row of bumps or each of the first rows of bumps is slightly below a corresponding second row of bumps. The staggered bumps prevent the LCD panel from generating picture distortion and gravity mura, even when the liquid crystal is weighty.
Abstract:
The present invention discloses a liquid crystal display with a narrow frame area. The liquid crystal display comprises a first substrate, plural scan line metal layers and plural data line metal layers formed on the first substrate, a second substrate attached to the first substrate by applying a seal at a periphery of one of the first substrate and the second substrate, and an opaque layer formed on the second substrate at the inside of the seal. In which, the scan line metal layers and the data line metal layers extend to the outside of the seal, and overlap with each other to form an integrated black matrix on the first substrate, which overlaps with the opaque layer on the second substrate so as to prevent a light leakage in an overlapped area thereof and narrow down the frame area.
Abstract:
An organic light emitting diode is provided. The organic light emitting diode includes a substrate, an electrode structure formed on said substrate, an organic layer formed on said electrode structure and a transparent electrode structure having at least one transparent dielectric layer with a relatively higher refraction index and deposited on said organic layer by thermal evaporation.
Abstract:
An LCD panel testing method. The method comprises forming jump lines in a predetermined region on the substrate between the signal lines via mask design when forming TFT LCD arrays, and thus forming a plurality of signal-line groups each with two signal lines coupled by the jump lines. Thereupon, an array tester sequentially tests two pixels corresponding to the signal lines in the signal groups. If one of the feedback signals from the signal groups does not meet a predetermined standard, it is determined that one or both pixels in the signal group are defective. The defective pixel or pixels are then identified using an electronic microscope to test two pixels at the same time. In this way, the number of probe pins and tests performed is halved. The probe pin size is also thus less restrictive due to larger probe pin intervals. Consequently, yield is greatly increased.
Abstract:
A TFT array substrate and a process for manufacturing the same are provided. A plurality of TFTs in array are formed on a substrate. A gate insulating layer and a protection layer are sequentially formed to cover a pixel region of the substrate. A plurality of openings each of which has an undercut profile are formed in the gate insulating layer and the protection layer. Then, a transparent conductive layer is formed over the substrate. One of the two parts separated is located in a bottom of the opening and the other is on the protection layer, such that two parts of the transparent conductive layer disconnect and no junction there between occurs. The part of the transparent conductive layer in the bottom of the opening is referred to as a transparent pixel electrode. The part of the transparent conductive layer on the protection layer is connected to a common metal line to form a transparent common electrode. The transparent pixel electrode disconnects to but overlaps the protection layer
Abstract:
The present invention discloses a DRAM structure with multiple memory cells sharing the same bit-line contact. The DRAM structure of the present invention comprises: a substrate; an active region formed on the substrate, with a center region and a plurality of protrusion regions connecting to the two sides of the center region; a plurality of word-lines, disconnected from each other, each crossing the corresponding protrusion region; a plurality of channel regions, formed where the protrusion region overlaps with the word-lines; a plurality of source regions, formed at the outer areas of the channel regions; a sharing drain region, formed at the center region of the active region; a bit-line contact, formed on surface of the sharing drain region; a bit-line, crossing the center region and electrically connected to the sharing drain region via the bit-line contact; a plurality of capacitors, electrically connected to the source regions; and a plurality of metal lines, electrically connected to the corresponding word-lines.