公开(公告)号：US20050048898A1

公开(公告)日：2005-03-03

申请号：US10621391

申请日：2003-07-18

Applicant: Ta-Kuang Chang ,  Ya-Tuan Tseng ,  Lee-Zen Chen ,  Bing-Lin Lin ,  Li-Chieh Wang ,  Meil-Li Lee

Inventor： Ta-Kuang Chang ,  Ya-Tuan Tseng ,  Lee-Zen Chen ,  Bing-Lin Lin ,  Li-Chieh Wang ,  Meil-Li Lee

IPC: B08B15/02

CPC classification number: B08B15/023

Abstract: A clean bench providing a working space for technicians, in a clean room, to remove and trap particles from the surface of an object with a high-pressure spray gun or a vacuum suction unit. This clean bench has an isolated disposal working space to avoid the escape of particles from it; moreover, it conducts and traps them by the design of a particle-conducting basin and a fan-filter unit (FFU) in it.

Abstract translation: 一个干净的工作台，为技术人员提供工作空间，在洁净室内，用高压喷枪或真空抽吸装置从物体表面去除和捕获颗粒。 这个干净的工作台具有隔离的处理工作空间，以避免颗粒从中脱出; 此外，它通过设计颗粒传导盆和风扇过滤器单元（FFU）来进行捕获。

公开(公告)号：US20050030776A1

公开(公告)日：2005-02-10

申请号：US10935629

申请日：2004-09-07

Applicant: Yung-Lin Lin

Inventor： Yung-Lin Lin

IPC: H02M7/523 ,  H02M7/5387 ,  H05B41/282 ,  H05B41/285 ,  H05B41/392 ,  H02M3/335

CPC classification number: H05B41/3927 ,  H02M7/523 ,  H02M7/5387 ,  H02M2001/0048 ,  H02M2007/4815 ,  H05B41/2828 ,  H05B41/2855 ,  Y02B20/185 ,  Y02B70/1441 ,  Y02B70/1491

Abstract: A CCFL power converter circuit is provided using a high-efficiency zero-voltage-switching technique that eliminates switching losses associated with the power MOSFETs. An optimal sweeping-frequency technique is used in the CCFL ignition by accounting for the parasitic capacitance in the resonant tank circuit. Additionally, the circuit is self-learning and is adapted to determine the optimum operating frequency for the circuit with a given load. An over-voltage protection circuit can also be provided to ensure that the circuit components are protected in the case of open-lamp condition.

Abstract translation: 使用高效率零电压切换技术提供CCFL功率转换器电路，其消除与功率MOSFET相关的开关损耗。 通过考虑谐振回路中的寄生电容，在CCFL点火中使用最佳的扫频技术。 此外，电路是自学习的，并且适于确定具有给定负载的电路的最佳工作频率。 也可以提供过电压保护电路，以确保在开灯状态下保护电路部件。

公开(公告)号：US20050024380A1

公开(公告)日：2005-02-03

申请号：US10627763

申请日：2003-07-28

Applicant: Lin Lin ,  Chih-Chang Lai ,  Yung-Li Hsu

Inventor： Lin Lin ,  Chih-Chang Lai ,  Yung-Li Hsu

IPC: G09G5/02 ,  G09G5/39 ,  G09G5/393

CPC classification number: G09G5/02 ,  G09G5/39 ,  G09G5/393 ,  G09G2340/02

Abstract: A method for reducing random access memory (RAM) of an IC in display devices includes transforming a digital signal of a graphic data of three original colors (R, G, B) to digital signals of Y:Cb:Cr; taking one sample from two sample ratios of Y:Cb:Cr (4:2:0) or Y:Cb:Cr (4:2:2); storing in the RAM of a driving IC to reduce the RAM usage (with compressible data); then transforming the Y:Cb:Cr signals to three original colors (R, G, B) signal format to output image data, wherein Y represents brightness signal, and Cb and Cr represent color signals.

Abstract translation: 用于减少显示装置中的IC的随机存取存储器（RAM）的方法包括将三原色（R，G，B）的图形数据的数字信号变换为数字信号Y：Cb：Cr; 从Y：Cb：Cr（4：2：0）或Y：Cb：Cr（4：2：2）的两个采样比中取出一个样品; 存储在驱动IC的RAM中以减少RAM使用（具有可压缩数据）; 然后将Y：Cb：Cr信号转换为三原色（R，G，B）信号格式，输出图像数据，其中Y表示亮度信号，Cb和Cr表示彩色信号。

公开(公告)号：US20050018456A1

公开(公告)日：2005-01-27

申请号：US10919955

申请日：2004-08-17

Applicant: Yung-Lin Lin

Inventor： Yung-Lin Lin

IPC: H02J3/00 ,  H02J5/00 ,  H02M1/00 ,  H02M1/36 ,  H02M7/5387 ,  H02M7/5395

CPC classification number: H02M1/36 ,  H02J3/00 ,  H02J5/00 ,  H02M7/53871 ,  H02M7/5395

Abstract: A controller for controlling at least two power circuits comprises a pulse generator and a selector. The pulse generator generates a first pulse signal which is coupled to a first power circuit of the at least two power circuits for initiating the operation of the first power circuit. The first power circuit then outputs a second pulse signal to a second power circuit of the at least two power circuits to initiate the operation of the second power circuit. The selector generates a reference signal which is coupled to each of the at least two power circuits for indicating a number of power circuits controlled. The controller is used to control energy supplying to an electrical circuit comprising multiple inverters and is more particularly to provide phase shifts to the electrical circuit. Usually, the electrical circuit is applied to display devices, such as liquid crystal display monitors, liquid crystal display computers and liquid crystal display televisions.

Abstract translation: 用于控制至少两个电源电路的控制器包括脉冲发生器和选择器。 脉冲发生器产生第一脉冲信号，其耦合到至少两个电源电路的第一电源电路，用于启动第一电源电路的操作。 然后，第一电源电路将第二脉冲信号输出到至少两个电源电路的第二电源电路以启动第二电源电路的操作。 选择器产生参考信号，该参考信号耦合到至少两个电源电路中的每一个，用于指示受控的多个电源电路。 控制器用于控制向包括多个反相器的电路供电的能量，更具体地说是提供到电路的相移。 通常，将电路应用于液晶显示监视器，液晶显示电脑和液晶显示电视等显示装置。

公开(公告)号：US06806054B2

公开(公告)日：2004-10-19

申请号：US09826509

申请日：2001-04-05

Applicant: Karin Lehmann-Bruinsma ,  Chen W. Liaw ,  I-Lin Lin

Inventor： Karin Lehmann-Bruinsma ,  Chen W. Liaw ,  I-Lin Lin

IPC: G01N3353

CPC classification number: G01N33/74 ,  A61K38/00 ,  C07K14/705 ,  C07K14/723 ,  C07K2319/00 ,  G01N2333/726 ,  G01N2500/10

Abstract: The invention disclosed in this patent document relates to transmembrane receptors, more particularly to a human G protein-coupled receptor for which the endogenous ligand is known (“known GPCRs”), and most particularly to mutated (non-endogenous) versions of the known GPCRs for use, most preferably in screening assays for the direct identification of candidate compounds as inverse agonists, agonists and partial agonists.

Abstract translation: 本专利文献中公开的发明涉及跨膜受体，更具体地涉及内源性配体已知的人G蛋白偶联受体（“已知的GPCR”），最特别地涉及已知的突变的（非内源的）版本 GPCRs，最优选用于直接鉴定作为反向激动剂，激动剂和部分激动剂的候选化合物的筛选试验。

公开(公告)号：US06804129B2

公开(公告)日：2004-10-12

申请号：US10776417

申请日：2004-02-11

Applicant: Yung-Lin Lin

Inventor： Yung-Lin Lin

IPC: H02M3335

CPC classification number: H05B41/3927 ,  H02M7/523 ,  H02M7/5387 ,  H02M2001/0048 ,  H02M2007/4815 ,  H05B41/2828 ,  H05B41/2855 ,  Y02B20/185 ,  Y02B70/1441 ,  Y02B70/1491

Abstract: A CCFL power converter circuit is provided using a high-efficiency zero-voltage-switching technique that eliminates switching losses associated with the power MOSFETs. An optimal sweeping-frequency technique is used in the CCFL ignition by accounting for the parasitic capacitance in the resonant tank circuit. Additionally, the circuit is self-learning and is adapted to determine the optimum operating frequency for the circuit with a given load. An over-voltage protection circuit can also be provided to ensure that the circuit components are protected in the case of open-lamp condition.

Abstract translation: 使用高效率零电压切换技术提供CCFL功率转换器电路，其消除与功率MOSFET相关的开关损耗。 通过考虑谐振回路中的寄生电容，在CCFL点火中使用最佳的扫频技术。 此外，电路是自学习的，并且适于确定具有给定负载的电路的最佳工作频率。 也可以提供过电压保护电路，以确保在开灯状态下保护电路部件。

公开(公告)号：US06501234B2

公开(公告)日：2002-12-31

申请号：US09757265

申请日：2001-01-09

Applicant: Yung-Lin Lin ,  Yu-Cheng Chang ,  Bingwei Yao

Inventor： Yung-Lin Lin ,  Yu-Cheng Chang ,  Bingwei Yao

IPC: H05B3702

CPC classification number: H02M1/36 ,  H02J1/14 ,  H02M2001/008 ,  H05B41/3927

Abstract: A sequential burst mode regulation system to deliver power to a plurality of loads. In the exemplary embodiments, the system of the present invention generates a plurality of phased pulse width modulated signals from a single pulse width modulated signal, where each of the phased signals regulates power to a respective load. Exemplary circuitry includes a PWM signal generator, and a phase delay array that receives a PWM signal and generates a plurality of phased PWM signals which are used to regulate power to respective loads. A frequency selector circuit can be provided that sets the frequency of the PWM signal using a fixed or variable frequency reference signal.

公开(公告)号：US06184092B2

公开(公告)日：2001-02-06

申请号：US09444988

申请日：1999-11-23

Applicant: Mao-song Tseng ,  Rong-ching Chen ,  Su-wen Chang ,  Chin-lin Lin

Inventor： Mao-song Tseng ,  Rong-ching Chen ,  Su-wen Chang ,  Chin-lin Lin

IPC: H01L21336

Abstract: A method for forming a self-aligned contact for a trench DMOS transistor comprises: providing a semiconductor substrate; etching a trench into the semiconductor substrate at a selected location on the surface of the semiconductor substrate; forming a first dielectric layer that covers the semiconductor substrate and walls of the trench; forming a plug in the trench, which comprises a step of depositing a semiconductor layer that covers the semiconductor substrate and fills in the trench, and a step of etching the semiconductor layer until the plug is below the trench for about 0.2 to 0.3 micron; forming a second dielectric layer on the plug; and forming a conductive layer over the second dielectric layer and the surface of the semiconductor substrate for ohmic contact regions.

Abstract translation: 用于形成沟槽DMOS晶体管的自对准接触的方法包括：提供半导体衬底; 在所述半导体衬底的表面上的选定位置处将沟槽蚀刻到所述半导体衬底中; 形成覆盖半导体衬底和沟槽壁的第一介电层; 在沟槽中形成插塞，其包括沉积覆盖半导体衬底并填充在沟槽中的半导体层的步骤，以及蚀刻半导体层直到插塞在沟槽下方约0.2至0.3微米的步骤; 在所述插头上形成第二电介质层; 以及在第二电介质层和用于欧姆接触区域的半导体衬底的表面上形成导电层。

公开(公告)号：US6033589A

公开(公告)日：2000-03-07

申请号：US941713

申请日：1997-09-30

Applicant: Hsiang-Lin Lin

Inventor： Hsiang-Lin Lin

IPC: B05D1/00 ,  H01L21/00 ,  C09D5/20

CPC classification number: H01L21/6715 ,  B05D1/005 ,  H01L21/67051

Abstract: The present invention discloses a method for depositing a coating layer on an article without edge bead formation by integrating the steps of an edge bead rinsing process with a coating spin-out process such that an edge portion of the wafer can be efficiently cleaned with a cleaning solvent when the coating material is still in its liquid state. While the present invention method can be applied to any coating materials and to any coated substrate, it is particularly suitable for cleaning a spin-on-glass material from a semiconductor wafer such that the wafer edge is not coated with a SOG material and thus particulate contamination caused by cracked SOG from the wafer edge can be avoided.

Abstract translation: 本发明公开了一种用于在没有边缘珠形成的物品上沉积涂层的方法，该方法是通过将边缘珠清洗工艺与涂层旋转工艺相结合的步骤整合在一起，使得可以用清洁剂有效地清洁晶片的边缘部分 当涂料仍处于其液态时，溶剂即可。 虽然本发明的方法可以应用于任何涂层材料和任何涂覆的基底，但是特别适用于从半导体晶片清洗旋涂玻璃材料，使得晶片边缘未涂覆有SOG材料，因此颗粒 可以避免由晶片边缘破裂的SOG引起的污染。

公开(公告)号：US5994219A

公开(公告)日：1999-11-30

申请号：US90498

申请日：1998-06-04

Applicant: Hsiang-Lin Lin ,  Han-Chung Chen

Inventor： Hsiang-Lin Lin ,  Han-Chung Chen

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/441

CPC classification number: H01L21/28512 ,  H01L21/76838

Abstract: A new method of metal deposition with reduced metal residue after metal etching by cooling the wafer before metal deposition is described. A first patterned conducting layer is provided overlying a dielectric layer on the surface of a semiconductor substrate. The wafer is cooled to a temperature of less than about 20.degree. C. Thereafter, a metal layer is deposited overlying the first patterned conducting layer. The metal layer is etched away where it is not covered by a mask to complete formation of the metal line. Cooling of the wafer before metal deposition decreases the metal residue found after metal etching.

Abstract translation: 描述了在金属沉积之前通过冷却晶片在金属蚀刻之后金属沉积减少的新方法。 第一图案化导电层设置在半导体衬底的表面上覆盖介电层。 将晶片冷却至低于约20℃的温度。此后，沉积覆盖第一图案化导电层的金属层。 金属层被蚀刻掉，其未被掩模覆盖以完成金属线的形成。 在金属沉积之前，晶片的冷却减少金属蚀刻后发现的金属残留。