NOISE-LOWERING POWER FET DRIVER
    1.
    发明公开

    公开(公告)号:US20240364234A1

    公开(公告)日:2024-10-31

    申请号:US18308342

    申请日:2023-04-27

    CPC classification number: H02M7/53871 H02M1/088

    Abstract: In described examples, an integrated circuit includes first and second transistors, a switch, a capacitor, a resistor, and first and second comparators. A first terminal of the switch is coupled to a first terminal of the resistor. A second terminal of the switch is coupled to a second terminal of the resistor, a first terminal of the capacitor, and a gate of the first transistor. The first comparator is configured to receive at the first input a first reference voltage, and an output of the first comparator is coupled to a gate of the second transistor. The second comparator is configured to receive at the first input a second reference voltage. A second input of the second comparator is coupled to a second input of the first comparator. An output of the second comparator is coupled to a control input of the switch.

    GRID-CONNECTED CONTROL METHOD AND SYSTEM FOR GRID-FORMING CONVERTER WITHOUT GRID-SIDE VOLTAGE SENSOR

    公开(公告)号:US20240364116A1

    公开(公告)日:2024-10-31

    申请号:US18620094

    申请日:2024-03-28

    CPC classification number: H02J3/44 H02M7/53871

    Abstract: The present disclosure pertains to the field of power electronics technologies, and provides a grid-connected control method and system for a grid-forming converter without a grid-side voltage sensor. The grid-connected control method includes: performing coordinate transformation on a phase of a three-phase capacitor voltage sampled by a phase-locked loop (PLL) to obtain a first phase; in response to control of a first pulse width modulation (PWM) pulse signal, introducing a reference phase, and performing negative feedback regulation on a difference between the reference phase and the first phase to obtain a second phase; and in response to control of a second PWM pulse signal, performing a modulo operation on a difference between the reference phase and the second phase to obtain a third phase, where the third phase is used to replace a phase of the PLL to perform coordinate transformation of a system.

    CONTROLLER FOR A POWER CONVERTER AND A METHOD OF CONTROLLING A POWER CONVERTER

    公开(公告)号:US20240333177A1

    公开(公告)日:2024-10-03

    申请号:US18193919

    申请日:2023-03-31

    Applicant: NXP USA, Inc.

    CPC classification number: H02M7/53871 H02M1/0003

    Abstract: A controller for a power converter includes a generator module configured to generate a sequence of pulses each having a width defined by a rise moment, R, and fall moment, F, stored in respective RM and FM registers. The sequence of pulses have a repetition rate, T, that is modulated by a repetition period, RP, value stored in a RP register. A memory of the controller has tables of R values, F values and RP values configured to be written into the generator module RM, FM and TM registers respectively. A direct memory access (DMA) module of the controller is configured to write R, F and RP values from the respective memory table into the RM, FM, and TM registers respectively, in response to a DMA trigger. A core coupled to the DMA module is configured to write the R, F and RP values into the memory table.

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