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公开(公告)号：US20210067177A1
公开(公告)日：2021-03-04
申请号：US17010351
申请日：2020-09-02
Inventor： Fabrice ROMAIN , Mathieu LISART , Patrick Arnould
Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.
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公开(公告)号：US20210019448A1
公开(公告)日：2021-01-21
申请号：US16928901
申请日：2020-07-14
Inventor： Marc BENVENISTE , Fabien JOURNET , Fabrice MARINET
Abstract: Authenticating a device using processing circuitry that generates fingerprints based on states of a plurality of nodes that are coupled to a plurality of circuits. A first fingerprint is generated at a first time based on first states of the plurality of nodes. A second fingerprint is generated at a second time based on second states of the plurality of nodes, the first fingerprint influencing the second states. Electronic data is obtained from the device to be authenticated. The electronic data is compared with a fingerprint generated and a determination whether to authorize operation of the device is made based on a result of the comparison.
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公开(公告)号：US20210006256A1
公开(公告)日：2021-01-07
申请号：US16918940
申请日：2020-07-01
Applicant: STMicroelectronics SA , STMicroelectronics (Alps) SAS
Inventor： Stéphane Le Tual , David Duperray , Jean-Pierre Blanc
Abstract: A sampling circuit includes a metal oxide semiconductor (MOS) transistor that includes a third metallization receiving a reference voltage between a first metallization coupled to a source region of the transistor and a second metallization coupled to a drain region of the transistor.
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公开(公告)号：US20200212927A1
公开(公告)日：2020-07-02
申请号：US16709391
申请日：2019-12-10
Applicant: STMicroelectronics SA , STMicroelectronics (Alps) SAS
Inventor： Stephane LE TUAL , Jean-Pierre BLANC , David DUPERRAY
Abstract: An acquisition stage receives a digital input signal and generates therefrom a first digital signal and a second digital signal complementary thereto. First and second processing stages receive the first and second digital signals and generate therefrom first and second analog signals in time with first and second complementary clock signals. An output stage generates an internal clock signal equivalent to one of: the first clock signal phase shifted by a duration of a transient occurring during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient occurring during a period of the second clock signal. The output stage produces an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level, and equal to the second analog signal when the internal clock signal is at a second logic level.
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公开(公告)号：US20200211607A1
公开(公告)日：2020-07-02
申请号：US16729056
申请日：2019-12-27
Inventor： Diana Moisuc , Christophe Laurencin
Abstract: In an embodiment, a method for protecting an electronic circuit includes: detecting a malfunction of the electronic circuit; executing a plurality of waves of countermeasures without interrupting an operation of the electronic circuit; and triggering a reset of the electronic circuit after executing the plurality of waves of countermeasures. An interval between two waves of countermeasures of the plurality of waves of countermeasures is variable.
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Patent Agency Ranking
96.发明授权公开(公告)号：US10673447B2
公开(公告)日：2020-06-02
申请号：US16269303
申请日：2019-02-06
Applicant: STMicroelectronics (Alps) SAS
Inventor： Laurent Vaccariello
Abstract: An N-bit type charge redistribution analog-to-digital conversion device includes an input terminal configured to receive an input signal and coupled via a line to an output terminal. The output terminal is configured to be coupled to a comparator. The device further includes three reference potential sources of different values and a network of capacitors, where a first terminal of each capacitor is coupled to the line, and where a second terminal of each capacitor is coupled to switching circuit configured for coupling the second terminal of each capacitor to one of the reference potentials.
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公开(公告)号：US10607949B2
公开(公告)日：2020-03-31
申请号：US15607780
申请日：2017-05-30
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics SA
Inventor： Yves Mazoyer , Philippe Galy , Philippe Sirito-Olivier
Abstract: Electrostatic discharge (ESD) protection is provided by a circuit including a resistor having a first terminal and a second terminal, a zener diode having a cathode terminal directly connected to said first terminal and an anode terminal directly connected to a third terminal, and a clamp diode having a cathode terminal directly connected to said second terminal and an anode terminal directly connected to said third terminal.
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公开(公告)号：US10593361B2
公开(公告)日：2020-03-17
申请号：US15867223
申请日：2018-01-10
Inventor： Jonathan Cottinet , Jean Claude Bini
Abstract: A method for transmitting and/or receiving a potential aggressor audio signal includes a transmission and/or a reception of successive groups of data timed by a first clock signal within respective successive frames synchronized by a second clock signal. In the presence of a risk of interference of the potential aggressor audio signal with a different, potential victim, signal, during the transmission or reception of the potential aggressor audio signal, the frequency of the first clock signal is modified while keeping the frequency of the second clock signal unchanged.
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公开(公告)号：US20200073051A1
公开(公告)日：2020-03-05
申请号：US16549843
申请日：2019-08-23
Inventor： Charles Baudot , Sylvain Guerber , Patrick Le Maitre
IPC: G02B6/125
Abstract: In one embodiment, a waveguide includes an upstream portion, a downstream portion, and an intermediate portion between the upstream portion and the downstream portion. A first band is disposed on an insulating layer, the first band oriented along a first direction. A first lateral strip and a second lateral strip are disposed on either side of the first band, the first lateral strip and the second lateral strip being thinner or interrupted along the intermediate portion.
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公开(公告)号：US10560092B2
公开(公告)日：2020-02-11
申请号：US16274844
申请日：2019-02-13
Inventor： Vanni Poletto , David F. Swanson , Giovanni Luca Torrisi , Laurent Chevalier
IPC: H03K17/687 , G01R19/165 , G05B11/42
Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.
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