公开(公告)号：US20040114542A1

公开(公告)日：2004-06-17

申请号：US10318423

申请日：2002-12-13

Applicant: TIOGA TECHNOLOGIES LTD ,  STMicroelectronics Ltd.

Inventor： Danny Stopler

IPC: H04B003/20

CPC classification number: H04B3/23 ,  H04M9/082

Abstract: A receiver for receiving an incoming signal over a communication medium includes an echo canceller, which is adapted to receive an outgoing signal transmitted over the communication medium, and to process the outgoing signal using a set of variable processing coefficients in order to generate an echo cancellation signal. A summer combines the incoming signal with the echo cancellation signal so as to generate an echo-cancelled signal. An equalizer applies an equalization operation to the echo-cancelled signal so as to generate an equalized signal. A residual echo cancellation circuit processes the equalized signal so as to adaptively update the variable processing coefficients of the echo canceller.

Abstract translation: 用于通过通信介质接收输入信号的接收机包括回波消除器，其适于接收通过通信介质发送的输出信号，并且使用一组可变处理系数来处理输出信号，以便产生回声消除 信号。 夏天将输入信号与回波消除信号相结合，以产生回声消除信号。 均衡器对回波消除信号施加均衡操作，以产生均衡的信号。 残余回波消除电路处理均衡信号，以自适应地更新回波消除器的可变处理系数。

公开(公告)号：US20030218195A1

公开(公告)日：2003-11-27

申请号：US10401276

申请日：2003-03-27

Applicant: STMicroelectronics Ltd.

Inventor： Jeff Raynor

IPC: H01L031/062 ,  H01L031/113

CPC classification number: H01L27/14609

Abstract: A solid state image sensor has an array of pixels formed on an epitaxial layer on a substrate. Each pixel is relatively large so that it has a high light collecting ability, such as 40-60 nullm, but the pixel photodiode is relatively small so that it has a low capacitance, such as 4-6 nullm. Active elements of the pixel photodiode are formed in wells that are spaced away from the pixel photodiode so that the latter is surrounded by epitaxial material.

Abstract translation: 固态图像传感器具有形成在衬底上的外延层上的像素阵列。 每个像素相对较大，因此其具有高的聚光能力，例如40-60μm，但像素光电二极管相对较小，因此其具有低电容，例如4-6μm。 像素光电二极管的有源元件形成在与像素光电二极管间隔开的阱中，使得其被外延材料包围。

公开(公告)号：US20030164443A1

公开(公告)日：2003-09-04

申请号：US10350166

申请日：2003-01-23

Applicant: STMicroelectronics Ltd

Inventor： Robert Henderson

IPC: H01L027/00

CPC classification number: H04N5/3653 ,  H04N5/3745

Abstract: An image sensor includes pixels which are of the four-transistor, PIN photodiode type. In each pixel, the charge on a photodiode is transferred by a transfer gate to a sensing node. Readout of reset and read voltages is via an amplifier. A gain capacitor is connected in feedback across the amplifier. Read and reset gates are controlled so that the pixel is reset to a virtual ground voltage controlled by the gain capacitor. This is independent of the pixel parasitic capacitance.

Abstract translation: 图像传感器包括四晶体管PIN光电二极管类型的像素。 在每个像素中，光电二极管上的电荷通过传输门传输到感测节点。 通过放大器读出复位和读取电压。 增益电容器连接在放大器的反馈中。 读取和复位门被控制，使得像素被复位到由增益电容器控制的虚拟接地电压。 这与像素寄生电容无关。

公开(公告)号：US20030080340A1

公开(公告)日：2003-05-01

申请号：US10265289

申请日：2002-10-04

Applicant: STMicroelectronics Ltd.

Inventor： Robert Henderson ,  Purcel Matthew ,  Jonathan Ephriam David Hurwitz

IPC: H01L029/04

CPC classification number: H04N5/3575 ,  H04N5/3653 ,  H04N5/378

Abstract: An active pixel array has the signal output of each pixel connected to a first column conductor, and a reset switch connected to a second column conductor. The first and second column conductors are connected to a read-reset amplifier. The read-reset amplifier operates in a first mode in which a reset voltage is applied to the second column line, and in a second mode in which pixel output signals are buffered from the first column line. The read-reset amplifier can also operate as a comparator forming part of an ADC circuit.

Abstract translation: 有源像素阵列具有连接到第一列导体的每个像素的信号输出，以及连接到第二列导体的复位开关。 第一和第二列导体连接到读 - 复位放大器。 读取复位放大器以第一模式工作，其中复位电压施加到第二列线，并且在第二模式中，其中像素输出信号从第一列线被缓冲。 读取复位放大器也可以作为形成ADC电路的一部分的比较器来工作。

公开(公告)号：US20030071666A1

公开(公告)日：2003-04-17

申请号：US10254443

申请日：2002-09-25

Applicant: STMicroelectronics Ltd.

Inventor： Toby Bailey

IPC: H03K004/06

CPC classification number: H03K4/026

Abstract: A ramp generator includes a resistance ladder supplied with a constant current. Switches are closed in sequence by a shift register to provide a stepped ramp output. The constant current is controlled by referencing an on-chip bandgap voltage that is used as an input to a feedback circuit controlling current through a reference resistor ladder.

Abstract translation: 斜坡发生器包括提供恒定电流的电阻梯。 开关按顺序由移位寄存器闭合，以提供阶梯式斜坡输出。 通过参考用作控制通过参考电阻梯的电流的反馈电路的输入的片上带隙电压来控制恒定电流。

公开(公告)号：US20030012282A1

公开(公告)日：2003-01-16

申请号：US10134662

申请日：2002-04-29

Applicant: STMicroelectronics Ltd.

Inventor： Paul Sathya Chelladurai ,  Arshad Ahmed ,  Soumitra Kumar Nandy

IPC: H04N007/12

CPC classification number: H04N19/53 ,  H04N19/14 ,  H04N19/194 ,  H04N19/61

Abstract: A method for efficient low power motion estimation of a digital video image is provided in which processing requirements are reduced based upon the content being processed. The method performs motion estimation of a current video image using a search window of a previous video image. The method may include forming mean pyramids of a reference macroblock and the search area and a full search at a lowest resolution. A number of candidate motion vectors (CMVs) propagated to lower levels may be dependent on a quantized average deviation estimate (QADE) of a current macroblock and the maximum distortion band obtained during training for that QADE value at that particular level. Training over a sequence may be triggered at the beginning of every sequence. This training technique may be used to determine the value of the maximum distortion band for all QADEs of the macroblocks occurring over the training frames.

Abstract translation: 提供了一种用于数字视频图像的有效低功率运动估计的方法，其中基于正在处理的内容来减少处理要求。 该方法使用先前视频图像的搜索窗口来执行当前视频图像的运动估计。 该方法可以包括以最低分辨率形成参考宏块的平均金字塔和搜索区域和全搜索。 传播到较低级别的多个候选运动矢量（CMV）可以取决于当前宏块的量化平均偏差估计（QADE）和在该特定级别处针对该QADE值的训练期间获得的最大失真频带。 在序列开始时可能会触发序列的训练。 该训练技术可用于确定在训练帧上发生的宏块的所有QADE的最大失真频带的值。

公开(公告)号：US20030005402A1

公开(公告)日：2003-01-02

申请号：US10186314

申请日：2002-06-28

Applicant: STMicroelectronics Ltd.

Inventor： Ankur Bal

IPC: G06F017/50

CPC classification number: H03K19/1776 ,  H03K19/17736 ,  H03K19/17744

Abstract: A system for simplifying the programmable memory-to-logic interface in field programmable gate arrays (FPGAs) is provided. An interface may be used to isolate the general purpose routing architecture for intra-programmable logic blocks (PLBs) from the random access memory (RAM) address lines, data lines, and control lines. The PLBs and the input-output resources of the FPGA access the embedded memory (or RAM) using dedicated direct interconnects. Certain of these direct interconnects may originate from PLBs in the vicinity of the RAM. The remainder run between the input-output (IO) pads/routing and the RAM blocks. A bus routing architecture is also provided to combine the memories to emulate larger RAM blocks. This bus routing provides interconnection among RAM blocks and is isolated from the PLB routing resources.

Abstract translation: 提供了一种用于简化现场可编程门阵列（FPGA）中的可编程存储器到逻辑接口的系统。 可以使用接口来隔离来自随机存取存储器（RAM）地址线，数据线和控制线的可编程逻辑块（PLB）的通用路由架构。 FPGA的PLB和输入输出资源使用专用直接互连访问嵌入式存储器（或RAM）。 这些直接互连中的某些可能来自RAM附近的PLB。 剩余部分在输入 - 输出（IO）焊盘/路由和RAM块之间运行。 还提供总线路由架构以组合存储器以模拟较大的RAM块。 该总线路由提供RAM块之间的互连，并与PLB路由资源隔离。

公开(公告)号：US20020114200A1

公开(公告)日：2002-08-22

申请号：US10072458

申请日：2002-02-07

Applicant: STMicroelectronics Ltd.

Inventor： Ankur Bal

IPC: G11C007/00

CPC classification number: H03K19/17776

Abstract: A system for relatively rapidly configuring reconfigurable devices with a plurality of latches is provided. The number of clock cycles for loading the configuration data may be reduced by a substantial amount, and the fidelity of data loaded into the configuration latches may be relatively high. The invention also incorporates procedures for configuring multiple reconfigurable devices, which are similar to daisy chaining techniques.

Abstract translation: 提供了一种用于相对快速地配置具有多个锁存器的可重新配置设备的系统。 用于加载配置数据的时钟周期的数量可以减少大量，并且加载到配置锁存器中的数据的保真度可能相对较高。 本发明还包括用于配置多个可重新配置设备的过程，其类似于菊花链技术。

公开(公告)号：US20020114025A1

公开(公告)日：2002-08-22

申请号：US09993387

申请日：2001-11-16

Applicant: STMicroelectronics Ltd

Inventor： Jeffrey Raynor ,  Peter Denyer ,  Jonathan Ephriam David Hurwitz

IPC: H04N001/46

CPC classification number: H04N5/37452 ,  H04N5/353 ,  H04N5/3575 ,  H04N5/378

Abstract: An image plane includes a plurality of pixels. Each pixel comprises a photodiode and two transistors, and each pixel is connected by a signal bus to a respective storage node located off the image plane. Each storage node comprises two capacitors and associated switches. One of the transistors applies a reset pulse to the pixel, and the other transistor connects the pixel to a given conductor of the signal bus, which is then connected to the storage node. The pixel transistors can be operated simultaneously, and the sensed values can subsequently be transferred from the storage nodes sequentially.

Abstract translation: 图像平面包括多个像素。 每个像素包括光电二极管和两个晶体管，并且每个像素通过信号总线连接到位于图像平面外的相应存储节点。 每个存储节点包括两个电容器和相关联的开关。 其中一个晶体管将复位脉冲施加到像素，另一个晶体管将像素连接到信号总线的给定导体，该导体然后连接到存储节点。 像素晶体管可以同时操作，并且随后可以从存储节点依次传送感测值。

公开(公告)号：US20020113618A1

公开(公告)日：2002-08-22

申请号：US10072461

申请日：2002-02-07

Applicant: STMicroelectronics Ltd.

Inventor： Ankur Bal

IPC: H03K019/173

CPC classification number: H03K19/17748 ,  H03K19/17728 ,  H03K19/17736

Abstract: A programmable logic device may include a programmable interconnect structure and a plurality of configurable logic elements including data latches interconnected by the interconnect structure. At least one of the configurable logic elements may be configurable as both a shift register and a lookup table. Also, the shift register may be enabled to operate as a bi-directional shift register by the inclusion of a first circuit for configuring the data latches either as series-connected inverters during a shift operation or as data latches after each shift operation. A second circuit for selecting a direction of shifting may also be included, as well as a third circuit for supplying data to the input of the shift register as determined by the direction of shifting.

Abstract translation: 可编程逻辑器件可以包括可编程互连结构以及包括通过互连结构互连的数据锁存器的多个可配置逻辑元件。 可配置逻辑元件中的至少一个可以被配置为移位寄存器和查找表。 此外，移位寄存器可以通过在移位操作期间包括用于配置数据锁存器作为串联连接的反相器的第一电路或者在每个移位操作之后的数据锁存器中而被允许作为双向移位寄存器操作。 还可以包括用于选择移位方向的第二电路，以及用于向由移位方向确定的移位寄存器的输入端提供数据的第三电路。