公开(公告)号：US20070188353A1

公开(公告)日：2007-08-16

申请号：US11735113

申请日：2007-04-13

申请人： Tin Lai ,  Wilson Wong ,  Sergey Shumarayev

发明人： Tin Lai ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03M7/00

CPC分类号： G11C7/12 ,  G11C7/1045 ,  H03M1/662

摘要： A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain. The plurality of register frames are serially linked and data within the data chain is shifted among the plurality of register frames. Through a time domain multiplexing scheme, the D2A can be shared by control knobs of the equalization circuit. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data within the data chain is shifting according to the clock period. A method for adjusting a signal through a bias circuit is also provided.

摘要翻译： 偏置电路包括产生表示用于调谐模拟信号的电压电平的输出的数模转换器（D 2A）。 D 2 A耦合到作为形成数据链的多个寄存器帧之一的主寄存器帧。 多个寄存器帧被串行链接，数据链内的数据在多个寄存器帧之间移位。 通过时域复用方案，D 2 A可由均衡电路的控制旋钮共享。 偏置电路包括还耦合到主寄存器框架的解码器。 还包括一个输出使能逻辑模块。 当数据链中的数据根据​​时钟周期进行移位时，输出使能逻辑模块确定主寄存器何时具有完整的数据集。 还提供了一种通过偏置电路调整信号的方法。

公开(公告)号：US20070147478A1

公开(公告)日：2007-06-28

申请号：US11486581

申请日：2006-07-14

申请人： Tin Lai ,  Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat

发明人： Tin Lai ,  Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat

IPC分类号： H04B1/00

CPC分类号： H04B7/005 ,  H04L25/03006 ,  H04L25/061

摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies. For low frequency adjustment, user-programmable parameters control the normalized signal amplitude in the signal normalization block and the low frequency adjustment in the equalization block.

摘要翻译： 公开了一种用于调整从通信路径接收的信号的系统和方法。 接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。 接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。 在一个实施例中，控制块控制用于高频的均衡块中的频率调整。 对于低频调整，用户可编程参数控制信号归一化块中的归一化信号幅度和均衡块中的低频调整。

公开(公告)号：US20070140387A1

公开(公告)日：2007-06-21

申请号：US11312181

申请日：2005-12-20

申请人： Wilson Wong ,  Rakesh Patel ,  Sergey Shumarayev ,  Tin Lai

发明人： Wilson Wong ,  Rakesh Patel ,  Sergey Shumarayev ,  Tin Lai

IPC分类号： H04L27/06

CPC分类号： H04B7/005 ,  H04L25/03006 ,  H04L25/061

摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.

摘要翻译： 公开了一种用于调整从通信路径接收的信号的系统和方法。 接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。 接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。 在一个实施例中，控制块控制用于高频而不是低频的均衡块中的频率调整。 对于低频调整，控制块控制信号归一化块中的归一化信号幅度。 以这种方式，在信号归一化块中执行低频内容的受控调整。

公开(公告)号：US20070041455A1

公开(公告)日：2007-02-22

申请号：US11361192

申请日：2006-02-23

申请人： Thungoc Tran ,  Sergey Shumarayev ,  Simardeep Maangat ,  Wilson Wong ,  Rakesh Patel

发明人： Thungoc Tran ,  Sergey Shumarayev ,  Simardeep Maangat ,  Wilson Wong ,  Rakesh Patel

IPC分类号： H04L25/00

CPC分类号： H04L1/243 ,  H04L25/03878

摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.

摘要翻译： 用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。 其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。 例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。 接收器电路的控制的各个方面可以是可编程的。

公开(公告)号：US07135885B2

公开(公告)日：2006-11-14

申请号：US11270229

申请日：2005-11-08

申请人： Wilson Wong ,  Sergey Shumarayev

发明人： Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03K19/03

CPC分类号： G01R31/31932 ,  G01R31/3167 ,  H03K5/1252 ,  H03K19/003 ,  H04L25/0292

摘要： A dynamically adjustable signal detector receives a differential input signal and outputs a signal indicative of whether a valid signal is being received based on dynamically adjustable threshold settings. The threshold settings can include differential voltage, peak power, average power, or other suitable settings, and can have a dynamically adjustable value for a selected threshold setting. The threshold settings and the value for a selected threshold setting can be set using control signals that are set by programmable logic resource circuitry, by soft intellectual property programmed into a programmable logic resource, by a processor, by circuitry external to a programmable logic resource, or by user input.

摘要翻译： 动态可调信号检测器接收差分输入信号，并且基于动态可调的阈值设置输出表示是否正在接收有效信号的信号。 阈值设置可以包括差分电压，峰值功率，平均功率或其他适当的设置，并且可以为所选阈值设置具有动态可调整的值。 可以使用由可编程逻辑资源电路设置的控制信号，通过编程到可编程逻辑资源中的软知识产权，由处理器，可编程逻辑资源外部的电路设置阈值设置和值， 或用户输入。

公开(公告)号：US07089444B1

公开(公告)日：2006-08-08

申请号：US10670147

申请日：2003-09-24

申请人： Kazi Asaduzzaman ,  Wilson Wong

发明人： Kazi Asaduzzaman ,  Wilson Wong

IPC分类号： G06F1/04

CPC分类号： H04L7/033 ,  H04L7/0008

摘要： Clock and data recovery circuitry is provided that is used in integrated circuits such as programmable logic device integrated circuits. The clock and data recovery circuitry may recover digital data and an embedded clock from a high-speed differential input data stream. The clock and data recovery circuitry may have automatic mode switching capabilities. When operated in reference mode, the clock and data recovery circuit may use a first phase-locked loop to lock onto a reference clock. When operated in data mode, the clock and data recovery circuit may use a second phase-locked loop to lock onto the phase of the differential data stream. A control circuit may automatically switch the clock and data recovery circuit between the reference mode and the data mode. Override signals may be used to force the clock and data recovery circuit out of the automatic mode and into either the reference or data mode.

摘要翻译： 提供了用于诸如可编程逻辑器件集成电路的集成电路中的时钟和数据恢复电路。 时钟和数据恢复电路可以从高速差分输入数据流恢复数字数据和嵌入时钟。 时钟和数据恢复电路可以具有自动模式切换功能。 当在参考模式下操作时，时钟和数据恢复电路可以使用第一锁相环锁定到参考时钟。 当在数据模式下操作时，时钟和数据恢复电路可以使用第二锁相环来锁定差分数据流的相位。 控制电路可以在参考模式和数据模式之间自动切换时钟和数据恢复电路。 可以使用覆盖信号强制时钟和数据恢复电路脱离自动模式并进入参考或数据模式。

公开(公告)号：US20060165204A1

公开(公告)日：2006-07-27

申请号：US11040342

申请日：2005-01-21

申请人： Sergey Shumarayev ,  Rakesh Patel ,  Wilson Wong ,  Tim Hoang

发明人： Sergey Shumarayev ,  Rakesh Patel ,  Wilson Wong ,  Tim Hoang

IPC分类号： H04L7/00 ,  H03D3/24

CPC分类号： H03L7/0998 ,  H03L7/081 ,  H03L7/087 ,  H03L7/113 ,  H03L7/14 ,  H04L7/0025 ,  H04L7/0083 ,  H04L7/033

摘要： The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.

公开(公告)号：US07053671B1

公开(公告)日：2006-05-30

申请号：US10871371

申请日：2004-06-17

申请人： Wilson Wong

发明人： Wilson Wong

IPC分类号： H03K5/22

CPC分类号： H03K19/018528

摘要： Circuitry is provided for converting differential digital data to single-ended digital data. Differential data signals have complementary pairs of signals that are referenced to each other. Single-ended signals are referenced to ground. The circuitry can be used on an integrated circuit to convert incoming differential data from a high-speed communications link to single-ended data for processing by internal logic on the integrated circuit. The operation of the circuitry can be stabilized using load circuitry that reduces temperature effects and jitter in the single-ended data.

摘要翻译： 提供电路用于将差分数字数据转换为单端数字数据。 差分数据信号具有彼此参考的互补的信号对。 单端信号参考地。 电路可用于集成电路，将来自高速通信链路的差分数据转换为单端数据，以便集成电路中的内部逻辑进行处理。 可以使用减少单端数据中的温度影响和抖动的负载电路来稳定电路的工作。

公开(公告)号：US20060066347A1

公开(公告)日：2006-03-30

申请号：US11270229

申请日：2005-11-08

申请人： Wilson Wong ,  Sergey Shumarayev

发明人： Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03K19/003

CPC分类号： G01R31/31932 ,  G01R31/3167 ,  H03K5/1252 ,  H03K19/003 ,  H04L25/0292

摘要： A dynamically adjustable signal detector receives a differential input signal and outputs a signal indicative of whether a valid signal is being received based on dynamically adjustable threshold settings. The threshold settings can include differential voltage, peak power, average power, or other suitable settings, and can have a dynamically adjustable value for a selected threshold setting. The threshold settings and the value for a selected threshold setting can be set using control signals that are set by programmable logic resource circuitry, by soft intellectual property programmed into a programmable logic resource, by a processor, by circuitry external to a programmable logic resource, or by user input.

公开(公告)号：US20050237082A1

公开(公告)日：2005-10-27

申请号：US11148046

申请日：2005-06-07

申请人： Sergey Shumarayev ,  Thomas White ,  Rakesh Patel ,  Wilson Wong

发明人： Sergey Shumarayev ,  Thomas White ,  Rakesh Patel ,  Wilson Wong

IPC分类号： H03K19/0185 ,  H03K19/177 ,  H04L25/02 ,  H03K19/003

CPC分类号： H03K19/17744 ,  H03K19/018585 ,  H03K19/1778 ,  H04L25/0272 ,  H04L25/0286

摘要： Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.