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    Clock data recovery circuitry and phase locked loop circuitry with dynamically adjustable bandwidths
    1.
    发明授权
    Clock data recovery circuitry and phase locked loop circuitry with dynamically adjustable bandwidths 有权
    时钟数据恢复电路和具有动态可调节带宽的锁相环电路

    公开(公告)号：US07149914B1

    公开(公告)日：2006-12-12

    申请号：US10672901

    申请日：2003-09-26

    申请人： Kazi Asaduzzaman ,  Wilson Wong ,  Sergey Shumarayev

    发明人： Kazi Asaduzzaman ,  Wilson Wong ,  Sergey Shumarayev

    IPC分类号： G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/24

    CPC分类号： H03L7/087 ,  H03L7/107 ,  H03L7/18 ,  H04L7/0008 ,  H04L7/033

    摘要： Clock data recovery (CDR) circuitry or phase locked loop (PLL) circuitry can be provided with a dynamically adjustable bandwidth. One CDR circuit or PLL circuit can be provided to support multiple systems or protocols, multiple parameter requirements for a given system or protocol, and changes in the input frequency or data rate within a given system or protocol. The parameters can include jitter (e.g., jitter tolerance, jitter transfer, jitter generation), source of dominant noise, and lock time. Control signals can be used to dynamically adjust the bandwidth of the CDR circuitry or PLL circuitry while the circuitry is processing data. The control signals can be set by a PLD, by a processor, by circuitry external to the PLD, or by user input.

    摘要翻译： 时钟数据恢复（CDR）电路或锁相环（PLL）电路可以提供动态可调的带宽。 可以提供一个CDR电路或PLL电路以支持多个系统或协议，给定系统或协议的多个参数要求，以及给定系统或协议内的输入频率或数据速率的变化。 这些参数可以包括抖动（例如，抖动容限，抖动传输，抖动产生），主要噪声源和锁定时间。 当电路正在处理数据时，控制信号可用于动态调整CDR电路或PLL电路的带宽。 控制信号可以由PLD，处理器，PLD外部的电路或用户输入来设置。

    Clock data recovery circuitry with dynamic support for changing data rates and a dynamically adjustable PPM detector
    2.
    发明授权
    Clock data recovery circuitry with dynamic support for changing data rates and a dynamically adjustable PPM detector 有权
    时钟数据恢复电路，动态支持数据速率的变化和动态调整的PPM探测器

    公开(公告)号：US07555087B1

    公开(公告)日：2009-06-30

    申请号：US12027909

    申请日：2008-02-07

    申请人： Kazi Asaduzzaman ,  Wilson Wong

    发明人： Kazi Asaduzzaman ,  Wilson Wong

    IPC分类号： H04L7/02

    CPC分类号： H04L7/0338 ,  H03L7/0807 ,  H03L7/087

    摘要： Clock data recovery (CDR) circuitry can be provided with dynamic support for changing data rates caused by the interfacing of different protocols. The CDR circuitry, which operates in reference clock mode and data mode, can be controlled by two control signals that signal the CDR circuitry to automatically switch between reference clock mode and data mode, to operate only in reference clock mode, or to operate only in data mode. The control signals can be set by a programmable logic device (PLD), by circuitry external to the PLD, or by user input. A dynamically adjustable parts per million (PPM) detector can also be provided in the CDR circuitry to signal when processing of data during the reference clock mode is completed.

    摘要翻译： 可以为时钟数据恢复（CDR）电路提供动态支持，以改变由不同协议的接口引起的数据速率。 以参考时钟模式和数据模式工作的CDR电路可以由两个控制信号控制，这两个信号指示CDR电路在参考时钟模式和数据模式之间自动切换，仅在参考时钟模式下工作，或仅在 数据模式。 控制信号可由可编程逻辑器件（PLD），PLD外部电路或用户输入设置。 也可以在CDR电路中提供动态可调节的百万分之一（PPM）检测器，以在参考时钟模式完成期间处理数据时发出信号。

    Clock and data recovery circuits
    3.
    发明授权
    Clock and data recovery circuits 有权
    时钟和数据恢复电路

    公开(公告)号：US07089444B1

    公开(公告)日：2006-08-08

    申请号：US10670147

    申请日：2003-09-24

    申请人： Kazi Asaduzzaman ,  Wilson Wong

    发明人： Kazi Asaduzzaman ,  Wilson Wong

    IPC分类号： G06F1/04

    CPC分类号： H04L7/033 ,  H04L7/0008

    摘要： Clock and data recovery circuitry is provided that is used in integrated circuits such as programmable logic device integrated circuits. The clock and data recovery circuitry may recover digital data and an embedded clock from a high-speed differential input data stream. The clock and data recovery circuitry may have automatic mode switching capabilities. When operated in reference mode, the clock and data recovery circuit may use a first phase-locked loop to lock onto a reference clock. When operated in data mode, the clock and data recovery circuit may use a second phase-locked loop to lock onto the phase of the differential data stream. A control circuit may automatically switch the clock and data recovery circuit between the reference mode and the data mode. Override signals may be used to force the clock and data recovery circuit out of the automatic mode and into either the reference or data mode.

    摘要翻译： 提供了用于诸如可编程逻辑器件集成电路的集成电路中的时钟和数据恢复电路。 时钟和数据恢复电路可以从高速差分输入数据流恢复数字数据和嵌入时钟。 时钟和数据恢复电路可以具有自动模式切换功能。 当在参考模式下操作时，时钟和数据恢复电路可以使用第一锁相环锁定到参考时钟。 当在数据模式下操作时，时钟和数据恢复电路可以使用第二锁相环来锁定差分数据流的相位。 控制电路可以在参考模式和数据模式之间自动切换时钟和数据恢复电路。 可以使用覆盖信号强制时钟和数据恢复电路脱离自动模式并进入参考或数据模式。

    Voltage-controlled oscillator methods and apparatus
    4.
    发明授权
    Voltage-controlled oscillator methods and apparatus 失效
    压控振荡器的方法和装置

    公开(公告)号：US07728674B1

    公开(公告)日：2010-06-01

    申请号：US11437558

    申请日：2006-05-19

    申请人： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

    发明人： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K3/35613 ,  H03K2005/00228 ,  H03K2005/00234

    摘要： Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.

    摘要翻译： 提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。 本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。 一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。 电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。 该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。

    Apparatus and methods for programmable slew rate control in transmitter circuits
    6.
    发明申请
    Apparatus and methods for programmable slew rate control in transmitter circuits 审中-公开
    发射机电路中可编程转换速率控制的装置和方法

    公开(公告)号：US20070013411A1

    公开(公告)日：2007-01-18

    申请号：US11183288

    申请日：2005-07-14

    申请人： Kazi Asaduzzaman ,  Sergey Shumarayev ,  Thungoc Tran ,  Wilson Wong ,  Rakesh Patel

    发明人： Kazi Asaduzzaman ,  Sergey Shumarayev ,  Thungoc Tran ,  Wilson Wong ,  Rakesh Patel

    IPC分类号： H03K19/094

    CPC分类号： H03K17/164

    摘要： High speed transmitter drivers and other types of driver circuitry may be required to produce output signals with variable slew rates. Driver circuitry and methods for providing variable slew rate control are described. Pre-driver circuitry with variable slew-rate may be used to supply signals with variable slew rate at the driver input. The driver and/or pre-driver circuits may include transistors with variable drive strengths. The driver and/or pre-driver circuits may also include selectably enabled stages for varying the circuit drive strength. The pre-driver circuitry may be delay matched to maintain signal quality. Other circuitry and methods are also described.

    摘要翻译： 可能需要高速变送器驱动器和其他类型的驱动电路来产生具有可变转换速率的输出信号。 描述了用于提供可变转换速率控制的驱动电路和方法。 可以使用具有可变转换速率的前驱动器电路在驱动器输入端提供具有可变转换速率的信号。 驱动器和/或预驱动器电路可以包括具有可变驱动强度的晶体管。 驱动器和/或预驱动器电路还可以包括用于改变电路驱动强度的可选择地启用的级。 预驱动器电路可以被延迟匹配以保持信号质量。 还描述了其它电路和方法。

    Voltage-controlled oscillator methods and apparatus
    7.
    发明授权
    Voltage-controlled oscillator methods and apparatus 有权
    压控振荡器的方法和装置

    公开(公告)号：US08120429B1

    公开(公告)日：2012-02-21

    申请号：US12787722

    申请日：2010-05-26

    申请人： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

    发明人： Tim Tri Hoang ,  Wilson Wong ,  Kazi Asaduzzaman ,  Simardeep Maangat ,  Sergey Shumarayev ,  Rakesh H. Patel

    IPC分类号： H03L7/00 ,  H03K3/03

    CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K3/35613 ,  H03K2005/00228 ,  H03K2005/00234

    摘要： Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.

    摘要翻译： 提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。 本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。 一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。 电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。 该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。

    Clock data recovery circuitry with dynamic support for changing data rates and a dynamically adjustable PPM detector
    9.
    发明授权
    Clock data recovery circuitry with dynamic support for changing data rates and a dynamically adjustable PPM detector 有权
    时钟数据恢复电路，动态支持数据速率的变化和动态调整的PPM探测器

    公开(公告)号：US07352835B1

    公开(公告)日：2008-04-01

    申请号：US10668900

    申请日：2003-09-22

    申请人： Kazi Asaduzzaman ,  Wilson Wong

    发明人： Kazi Asaduzzaman ,  Wilson Wong

    IPC分类号： H04L7/02

    CPC分类号： H04L7/0338 ,  H03L7/0807 ,  H03L7/087

    摘要： Clock data recovery (CDR) circuitry can be provided with dynamic support for changing data rates caused by the interfacing of different protocols. The CDR circuitry, which operates in reference clock mode and data mode, can be controlled by two control signals that signal the CDR circuitry to automatically switch between reference clock mode and data mode, to operate only in reference clock mode, or to operate only in data mode. The control signals can be set by a programmable logic device (PLD), by circuitry external to the PLD, or by user input. A dynamically adjustable parts per million (PPM) detector can also be provided in the CDR circuitry to signal when processing of data during the reference clock mode is completed.

    摘要翻译： 可以为时钟数据恢复（CDR）电路提供动态支持，以改变由不同协议的接口引起的数据速率。 以参考时钟模式和数据模式工作的CDR电路可以由两个控制信号控制，这两个信号指示CDR电路在参考时钟模式和数据模式之间自动切换，仅在参考时钟模式下工作，或仅在 数据模式。 控制信号可由可编程逻辑器件（PLD），PLD外部电路或用户输入设置。 也可以在CDR电路中提供动态可调节的百万分之一（PPM）检测器，以在参考时钟模式完成期间处理数据时发出信号。