公开(公告)号：US10288963B2

公开(公告)日：2019-05-14

申请号：US15643367

申请日：2017-07-06

Applicant: Apple Inc.

Inventor： Patrick B. Bennett ,  Kwang Soon Park ,  Chun-Yao Huang ,  Byung Duk Yang ,  Shih Chang Chang

IPC: G06F3/038 ,  G09G5/00 ,  G02F1/1362 ,  H01L27/12 ,  G09G3/20 ,  G02F1/1345

Abstract: A display may have an array of pixels arranged in rows and columns. Display driver circuitry may be provided along an edge of the display. Data lines that are associated with columns of the pixels may be used to distribute data from the display driver circuitry to the pixels. Gate lines in the display may each have a horizontal straight portion that extends along a respective row of the pixels and may each have one or more non-horizontal segments such as zigzag segments. The non-horizontal portion of each gate line may be connected to the horizontal straight portion of the gate line by a via. The non-horizontal portions may each have portions that are overlapped by portions of the data lines. Dummy gate line structures may be provided on the display that are not coupled to any of the pixels in the display.

公开(公告)号：US09869908B2

公开(公告)日：2018-01-16

申请号：US13644395

申请日：2012-10-04

Applicant: APPLE INC.

Inventor： Kyung-Wook Kim ,  Young Bae Park ,  Shih Chang Chang ,  Chun-Yao Huang ,  John Z. Zhong

IPC: G06F3/041 ,  G02F1/1343 ,  G09G3/36 ,  G02F1/136 ,  G02F1/1362

CPC classification number: G02F1/134363 ,  G02F2001/13606 ,  G02F2001/136218 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2300/0434

Abstract: A system and device for driving high resolution monitors while reducing artifacts thereon. Utilization of Z-inversion polarity driving techniques to drive pixels in a display reduces power consumption of the display but tends to generate visible horizontal line artifacts caused by capacitances present between the pixels and data lines of the display. By introducing a physical shield between the pixel and data line elements, capacitance therebetween can be reduced, thus eliminating the cause of the horizontal line artifacts. The shield may be a common voltage line (Vcom) of the display.

公开(公告)号：US20170294172A1

公开(公告)日：2017-10-12

申请号：US15631410

申请日：2017-06-23

Applicant: Apple Inc.

Inventor： Byung Duk Yang ,  Szu-Hsien Lee ,  Kyung-Wook Kim ,  Shih Chang Chang ,  Chun-Yao Huang ,  Hao-Lin Chiu

IPC: G09G3/36 ,  G02F1/1362 ,  G06F3/041 ,  G02F1/1345 ,  G02F1/1368 ,  G06F3/044 ,  G02F1/1333 ,  G02F1/1343

CPC classification number: G09G3/3648 ,  G02F1/13338 ,  G02F1/134309 ,  G02F1/1345 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/13456 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04104 ,  G06F2203/04112 ,  G09F9/30 ,  G09G3/3666 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2310/0281 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.

公开(公告)号：US09424793B2

公开(公告)日：2016-08-23

申请号：US14726312

申请日：2015-05-29

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Kwang Soon Park ,  Chin-Wei Lin ,  Chun-Yao Huang ,  Shih Chang Chang ,  Szu-Hsien Lee

IPC: H01L31/00 ,  G09G3/36 ,  G06F3/041

CPC classification number: G09G3/3648 ,  G06F3/0412 ,  G06F3/0416 ,  G09G2300/0408 ,  G09G2300/0842

Abstract: A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.

Abstract translation: 触摸屏显示器可以包括耦合到显示像素阵列的栅极线驱动器电路。 显示器可以具有帧内暂停（IFP）能力，其中可以在一个或多个帧内消隐间隔期间执行触摸或其它操作。 在一种合适的布置中，栅极驱动电路可以包括多个栅极线驱动器段，每个栅驱动器段由单独的栅极起始脉冲激活。 每个栅极起始脉冲只能在IFP间隔结束时释放。 在另一种合适的布置中，虚拟栅极驱动器单元可插入有源栅极驱动器单元中。 栅极输出信号可能在IFP内部传播通过虚拟栅极驱动器单元。 在另一种合适的布置中，每个有源栅极驱动器单元可以设置有缓冲部分，其保护栅极驱动器单元中的至少一些晶体管免受不期望的应力。

公开(公告)号：US20160098965A1

公开(公告)日：2016-04-07

申请号：US14504215

申请日：2014-10-01

Applicant: Apple Inc.

Inventor： Hao-Lin Chiu ,  Byung Duk Yang ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Shih Chang Chang ,  Szu-Hsien Lee

IPC: G09G3/36 ,  G02F1/1362 ,  H01L23/528 ,  G02F1/1368 ,  H01L27/12 ,  H01L23/522

CPC classification number: G09G3/3648 ,  G02F1/13338 ,  G02F1/134309 ,  G02F1/1345 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/13456 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04104 ,  G06F2203/04112 ,  G09F9/30 ,  G09G3/3666 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2310/0281 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.

Abstract translation: 显示器可以具有排列成行和列的像素阵列。 每个像素可以具有用于控制与该像素相关联的输出光量的晶体管。 晶体管可以是具有有源区的薄膜晶体管，第一和第二源极 - 漏极端子和栅极。 栅极线可用于将栅极控制信号分配到每行中的晶体管的栅极。 垂直于栅极线延伸的数据线可用于沿像素列分布图像数据。 栅极线可以连接到平行于数据线延伸的栅极线扩展。 数据线可以各自重叠相应的一个栅极线延伸。 通孔可用于将栅极线延伸部分连接到栅极线。 门线扩展可能都具有相同的长度。

公开(公告)号：US09182643B1

公开(公告)日：2015-11-10

申请号：US14494498

申请日：2014-09-23

Applicant: Apple Inc.

Inventor： Zhibing Ge ,  Enkhamgalan Dorjgotov ,  Cheng Chen ,  Lei Zhao ,  Chun-Yao Huang ,  Shih-Chang Chang ,  Shih-Chyuan Fan Jiang

IPC: G02F1/1343 ,  G02F1/136 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: G02F1/13624 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/136213 ,  G02F1/136277 ,  G02F1/1368

Abstract: A liquid crystal display may have a layer of liquid crystal material. The display may have an array of display pixel circuits. The display pixel circuits may each include a display pixel electrode that applies electric fields to a corresponding portion of the liquid crystal material. Thin-film transistor circuitry and other structures in the display pixels may control operation of the display pixels circuits. The thin-film transistor circuitry may be configured to handle operation of the display at multiple refresh rates. To accommodate multiple refresh rates, each pixel circuit may include a pair of transistors. A first transistor is used to apply data signals from a data line to the display pixel electrode. A storage capacitor is used to maintain the data signal on the electrode. The second transistor may be used to adjust the capacitance of the storage capacitor depending on the refresh rate of the display.

Abstract translation: 液晶显示器可以具有液晶材料层。 显示器可以具有显示像素电路的阵列。 显示像素电路可以各自包括将电场施加到液晶材料的对应部分的显示像素电极。 显示像素中的薄膜晶体管电路和其他结构可以控制显示像素电路的操作。 薄膜晶体管电路可以被配置为以多个刷新速率处理显示器的操作。 为了适应多个刷新率，每个像素电路可以包括一对晶体管。 第一晶体管用于将数据信号从数据线施加到显示像素电极。 使用存储电容器来维持电极上的数据信号。 第二晶体管可以用于根据显示器的刷新率来调整存储电容器的电容。

公开(公告)号：US09159288B2

公开(公告)日：2015-10-13

申请号：US13661839

申请日：2012-10-26

Applicant: Apple Inc.

Inventor： Shih Chang Chang ,  Young Bae Park ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Szu-Hsien Lee

IPC: G09G3/36

CPC classification number: G09G3/3677

Abstract: Gate line driver circuitry applies an output pulse to each of several gate lines for a display element array. The circuitry has a number of gate drivers each being coupled to drive a respective one of the gate lines. Each of the gate drivers has an output stage in which a high side transistor and a low side transistor are coupled to drive the respective gate line, responsive to at least one clock signal. A pull down transistor is coupled to discharge a control electrode of the output stage. A control circuit having a cascode amplifier is coupled to drive the pull down transistor as a function of a) at least one clock signal and b) feedback from the control electrode. Other embodiments are also described and claimed.

Abstract translation: 栅极线驱动器电路将输出脉冲施加到用于显示元件阵列的多个栅极线中的每一个。 电路具有多个栅极驱动器，每个栅极驱动器被耦合以驱动相应的一条栅极线。 每个栅极驱动器具有输出级，其中高侧晶体管和低侧晶体管耦合以响应于至少一个时钟信号驱动相应的栅极线。 耦合下拉晶体管以放电输出级的控制电极。 具有共源共栅放大器的控制电路被耦合以作为a）至少一个时钟信号和b）来自控制电极的反馈来驱动下拉晶体管。 还描述和要求保护其他实施例。

公开(公告)号：US20150269897A1

公开(公告)日：2015-09-24

申请号：US14726312

申请日：2015-05-29

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Kwang Soon Park ,  Chin-Wei Lin ,  Chun-Yao Huang ,  Shih Chang Chang ,  Szu-Hsien Lee

IPC: G09G3/36 ,  G06F3/041

CPC classification number: G09G3/3648 ,  G06F3/0412 ,  G06F3/0416 ,  G09G2300/0408 ,  G09G2300/0842

Abstract: A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.

Abstract translation: 触摸屏显示器可以包括耦合到显示像素阵列的栅极线驱动器电路。 显示器可以具有帧内暂停（IFP）能力，其中可以在一个或多个帧内消隐间隔期间执行触摸或其它操作。 在一种合适的布置中，栅极驱动电路可以包括多个栅极线驱动器段，每个栅驱动器段由单独的栅极起始脉冲激活。 每个栅极起始脉冲只能在IFP间隔结束时释放。 在另一种合适的布置中，虚拟栅极驱动器单元可插入有源栅极驱动器单元中。 栅极输出信号可能在IFP内部传播通过虚拟栅极驱动器单元。 在另一种合适的布置中，每个有源栅极驱动器单元可以设置有缓冲部分，其保护栅极驱动器单元中的至少一些晶体管免受不希望的应力。

公开(公告)号：US20150054799A1

公开(公告)日：2015-02-26

申请号：US14228098

申请日：2014-03-27

Applicant: Apple Inc.

Inventor： Shih Chang Chang ,  Ming-Chin Hung ,  Cheng-Ho Yu ,  Ting-Kuo Chang ,  Kyung-Wook Kim ,  Chun-Yao Huang ,  Szu-Hsien Lee ,  Yu-Cheng Chen ,  Hiroshi Osawa

IPC: G09G3/36

CPC classification number: H01L27/3262 ,  G02F1/13454 ,  G02F1/13624 ,  G02F1/1368 ,  G02F2001/13685 ,  G02F2202/104 ,  G09G3/3225 ,  G09G3/3611 ,  G09G3/3677 ,  G09G2320/043 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1255

Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.

Abstract translation: 电子设备可以包括在基板上具有显示像素阵列的显示器。 显示像素可以是液晶显示器中的有机发光二极管显示像素或显示像素。 在有机发光二极管显示器中，可以形成包括半导体氧化物薄膜晶体管，硅薄膜晶体管和电容器结构的混合薄膜晶体管结构。 电容器结构可以与半导体氧化物薄膜晶体管重叠。 有机发光二极管显示像素可以具有氧化物和硅晶体管的组合。 在液晶显示器中，显示驱动器电路可以包括硅薄膜晶体管电路，显示像素可以基于氧化物薄膜晶体管。 可以在形成硅晶体管栅极和氧化物晶体管栅极中使用单层或两层不同的栅极金属层。 硅晶体管可以具有与浮动栅极结构重叠的栅极。

公开(公告)号：US20140370655A1

公开(公告)日：2014-12-18

申请号：US14474433

申请日：2014-09-02

Applicant: Apple Inc.

Inventor： Ming-Chin Hung ,  Kyung Wook Kim ,  Young Bae Park ,  Hao-Lin Chiu ,  Chun-Yao Huang ,  Shih Chang Chang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/786 ,  H01L29/7869

Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.