公开(公告)号：US06285580B1

公开(公告)日：2001-09-04

申请号：US09441941

申请日：1999-11-17

Applicant: Ho Gia Phan ,  Derwin Jallice ,  Bin Li ,  Joseph Hoffman

Inventor： Ho Gia Phan ,  Derwin Jallice ,  Bin Li ,  Joseph Hoffman

IPC: G11C1100

CPC classification number: G11C11/4125

Abstract: A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, and a set of isolation transistors. The set of isolation transistors is coupled to the first set of cross-coupled transistors such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.

Abstract translation: 公开了一种用于静态随机存取存储器的单事件硬化存储单元。 单事件硬化存储单元包括第一组交叉耦合晶体管，第二组交叉耦合晶体管和一组隔离晶体管。 隔离晶体管的组合耦合到第一组交叉耦合晶体管，使得在交叉耦合晶体管和隔离晶体管之间形成两个反转路径。

公开(公告)号：US06282140B1

公开(公告)日：2001-08-28

申请号：US09589732

申请日：2000-06-08

Applicant: Ho Gia Phan ,  Bin Li

Inventor： Ho Gia Phan ,  Bin Li

IPC: G11C800

CPC classification number: G11C5/005 ,  G11C11/4125

Abstract: A multiplexor having a single event upset (SEU) hardened data keeper circuit is disclosed. The multiplexor includes a precharge transistor, an isolation transistor, an invertor, and an SEU immune storage cell. Both the gate of the precharge transistor and the gate of the isolation transistor are connected to a clock signal. The SEU immune storage cell has a first access node and a second access node. The first access node is complementary to the second access node. The first access node is connected to the precharge transistor and the second access node is connected to the isolation transistor. The invertor is coupled between the precharge transistor and the isolation transistor.

Abstract translation: 公开了具有单个事件镦锻（SEU）硬化数据保持器电路的多路复用器。 多路复用器包括预充电晶体管，隔离晶体管，反相器和SEU免疫存储单元。 预充电晶体管的栅极和隔离晶体管的栅极都连接到时钟信号。 SEU免疫存储单元具有第一接入节点和第二接入节点。 第一接入节点与第二接入节点互补。 第一接入节点连接到预充电晶体管，第二接入节点连接到隔离晶体管。 反相器耦合在预充电晶体管和隔离晶体管之间。

公开(公告)号：US06275080B1

公开(公告)日：2001-08-14

申请号：US09480454

申请日：2000-01-11

Applicant: Ho G. Phan ,  Derwin L. Jallice ,  Bin Li

Inventor： Ho G. Phan ,  Derwin L. Jallice ,  Bin Li

IPC: H03K3037

CPC classification number: H03K3/0375 ,  G11C5/005 ,  G11C11/4125

Abstract: An enhanced single event upset immune CMOS latch circuit is formed of a first and a second cross-coupled invertor having isolation transistors in the path coupling the drains of the transistors in the first invertor.

Abstract translation: 增强的单事件不安免疫CMOS锁存电路由第一和第二交叉耦合的反相器形成，其中第一和第二交叉耦合反相器在第一反相器中耦合晶体管的漏极的路径中具有隔离晶体管。

公开(公告)号：US06259643B1

公开(公告)日：2001-07-10

申请号：US09651155

申请日：2000-08-30

Applicant: Bin Li

Inventor： Bin Li

IPC: G11C702

CPC classification number: G11C11/4125

Abstract: A single event effect hardening technique for removing glitches in digital logic circuits is disclosed. The noise immune latch circuit includes a first input, a second input, and an output. The noise immune latch circuit includes a first set of two cross-coupled transistors, a second set of two cross-coupled transistors, a first set of isolation transistors, and a second set of isolation transistors. The cross-coupling is accomplished by connecting a gate of each transistor to a drain of another transistor in a same set. The first and second sets of isolation transistors are respectively connected to the first and second sets of cross-coupled transistors such that two inversion paths are formed including the two sets of cross-coupled transistors and the two sets of isolation transistors. The noise immune latch circuit changes from one state to another state only upon having incoming input signals of identical polarity being applied contemporaneously at both the first input and the second input. In addition, a delay element is connected between the incoming signals and the second input. The delay element provides a signal delay time equal to or greater than a pulse width of a noise induced glitch but less than a pre-determined pulse width of an incoming signal under normal operation.

Abstract translation: 公开了用于消除数字逻辑电路中的毛刺的单一事件效应强化技术。 噪声免疫锁定电路包括第一输入端，第二输入端和输出端。 噪声免疫锁存电路包括第一组两个交叉耦合晶体管，第二组两个交叉耦合晶体管，第一组隔离晶体管和第二组隔离晶体管。 交叉耦合是通过将每个晶体管的栅极连接到同一组中的另一个晶体管的漏极来实现的。 第一和第二组隔离晶体管分别连接到第一和第二组交叉耦合晶体管，使得形成包括两组交叉耦合晶体管和两组隔离晶体管的两个反转路径。 噪声免疫锁定电路仅在具有相同极性的输入输入信号同时在第一输入端和第二输入端施加时，从一种状态变化到另一状态。 此外，延迟元件连接在输入信号和第二输入之间。 延迟元件提供等于或大于噪声感应毛刺的脉冲宽度但小于在正常操作下的输入信号的预定脉冲宽度的信号延迟时间。

公开(公告)号：US06152249A

公开(公告)日：2000-11-28

申请号：US199585

申请日：1998-11-25

Applicant: Ke Mei Li ,  Wen Shi Wang ,  Bin Li ,  Qing Zhu

Inventor： Ke Mei Li ,  Wen Shi Wang ,  Bin Li ,  Qing Zhu

IPC: B62M6/65 ,  B62M6/55 ,  B62K11/00

CPC classification number: B62M6/55

Abstract: A kind of electric power-assisted bicycle is presented in the invention. Its characters consist in that: the electric-driving device 2 is composed of the flat motor installed in the shell and harmonic reducer; the shell body and storage battery are fixed in the middle of the frame; its center shaft crosses the flat motor and the harmonic reducer along with the axis line separately, and can rotate relatively to them; the mentioned flat motor is connected with the power-transmitting device through the harmonic reducer. The entire bicycle is lightweight and long-life, while it is also energy saving high efficient and can be conveniently assembled, used, carried and maintained.

Abstract translation: 本发明提出了一种电动辅助自行车。 其特征在于：电驱动装置2由安装在外壳中的扁平电机和谐波减速器组成; 壳体和蓄电池固定在框架的中间; 其中心轴分别与平面电机和谐波减速器一起穿过轴线，并可相对于它们旋转; 所述扁平电动机通过谐波减速器与发电装置连接。 整个自行车重量轻，使用寿命长，同时节能高效，方便组装，使用，携带和维护。

公开(公告)号：USD923106S1

公开(公告)日：2021-06-22

申请号：US29748048

申请日：2020-08-27

Applicant: Bin Li ,  Feifei Wang

Designer： Bin Li ,  Feifei Wang

公开(公告)号：US10582213B2

公开(公告)日：2020-03-03

申请号：US15025128

申请日：2013-10-14

Applicant: Microsoft Technology Licensing, LLC ,  Bin Li ,  Jizheng Xu ,  Gary J. Sullivan

Inventor： Bin Li ,  Jizheng Xu ,  Gary J. Sullivan

IPC: H04N19/593 ,  H04N19/52 ,  H04N19/56 ,  H04N19/91 ,  H04N19/82 ,  H04N19/57 ,  H04N19/86 ,  H04N19/70

Abstract: Innovations in intra block copy (“BC”) prediction mode facilitate intra BC prediction that is more effective in terms of rate-distortion performance and/or computational efficiency of encoding and decoding. For example, some of the innovations provide ways to select block vector (“BV”) values more effectively. Other innovations provide ways to encode/decode BV values more efficiently. Still other innovations address how to perform in-loop deblock filtering when a block has intra BC prediction mode, or address how to perform intra BC prediction when constrained intra prediction is enabled.

公开(公告)号：US09978482B2

公开(公告)日：2018-05-22

申请号：US13990093

申请日：2010-12-30

Applicant: Yongyong Yang ,  Geoffrey D. Brown ,  Manish Mundra ,  Bin Li ,  Journey Lu Zhu

Inventor： Yongyong Yang ,  Geoffrey D. Brown ,  Manish Mundra ,  Bin Li ,  Journey Lu Zhu

IPC: B29C47/02 ,  B29C47/86 ,  H01B13/14 ,  B29C47/28 ,  H01B7/00 ,  B29C47/00

CPC classification number: H01B13/14 ,  B29C47/0014 ,  B29C47/0016 ,  B29C47/025 ,  B29C47/28 ,  B29C47/864 ,  H01B7/00

Abstract: A die assembly (10) for extruding a polymeric coating onto a wire so as to impart a matte finish to the coating surface is provided. The die assembly (10) comprises: A) a die tip (13) comprising a tubular channel (22) through which a wire can pass, the channel (22) positioned along the central longitudinal axis (26) of the die assembly (10); B) a die body (12) comprising a trunk (15) and a head (16), the head (16) comprising a tubular channel (20), the head tubular channel (20) comprising a die land (21), the trunk (15) positioned about the die tip (13) so as to define an annular space (25) between the exterior surface (23) of the die tip (13) and the interior surface (24) of the trunk (15); C) a die holder (11) positioned about and in contact with the exterior surface (17) of the trunk (15); and D) a radiator (14) positioned about and in contact with the exterior surface (19) of the die land (21) of the die head (16).

公开(公告)号：US09749645B2

公开(公告)日：2017-08-29

申请号：US13530849

申请日：2012-06-22

Applicant: Bin Li ,  Jizheng Xu

Inventor： Bin Li ,  Jizheng Xu

IPC: H04N7/12 ,  H04N19/18 ,  H04N19/96 ,  H04N19/463 ,  H04N19/132

CPC classification number: H04N19/18 ,  H04N19/132 ,  H04N19/463 ,  H04N19/96

Abstract: Techniques for coding and deriving (e.g., determining) one or more coded-block-flags associated with video content are described herein. A coded-block-flag of a last node may be determined when coded-block-flags of preceding nodes are determined to be a particular value and when a predetermined condition is satisfied. In some instances, the predetermined condition may be satisfied when log2(size of current transform unit) is less than log2(size of maximum transform unit) or log2(size of current coding unit) is less than or equal to log2(size of maximum transform unit)+1. The preceding nodes may be nodes that precede the last node on a particular level in a residual tree.

公开(公告)号：US09689055B2

公开(公告)日：2017-06-27

申请号：US13598177

申请日：2012-08-29

Applicant: Shengen Zhang ,  Bin Li ,  Dean Pan ,  Jianjun Tian ,  Bo Liu

Inventor： Shengen Zhang ,  Bin Li ,  Dean Pan ,  Jianjun Tian ,  Bo Liu

IPC: C22B3/20 ,  C22B11/00 ,  C22B13/00 ,  C22B15/00 ,  C22B25/00 ,  C25C1/12 ,  C22B3/00 ,  C22B7/00

CPC classification number: C22B11/046 ,  C22B7/00 ,  C22B15/0056 ,  C25C1/12 ,  Y02P10/214 ,  Y02P10/22 ,  Y02P10/228 ,  Y02P10/236

Abstract: The invention related to the recycling field of waste printed circuit boards (WPCB), and especially involved a complete non-cyanogens wet process for green recycling of WPCB, which belonged to the field of recycle economy. In the invention, the process included that WPCB were broken by the jaw crusher, and then mixed copper powders and nonmetallic powders were separated by the method of air classification, the mixed copper powders were smelted and casted to get copper anode plates, the copper was purified by electrolytion, the valuable metals (such as copper, gold, silver, platinum and palladium, lead and tin) were recycled from the copper anode slime, and the waste water was recycled. The recovery ratio of all-metal was above 98%. The purity of the cathode copper was up to 4N level. The ratio of de-coppering was above 96%. The recovery ratio of gold was above 98.