公开(公告)号：US20090066424A1

公开(公告)日：2009-03-12

申请号：US11853905

申请日：2007-09-12

申请人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Masaaki Kaneko ,  Jieming Qi

IPC分类号： H03L7/00

CPC分类号： H03L7/18 ,  H03L7/0998

摘要： A programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. With the VCO, programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable.

摘要翻译： 提供了具有可调频率范围输出的可编程内插压控振荡器（VCO）。 利用VCO，可以利用基于可编程延迟单元的控制输入来修改尺寸的可编程延迟单元。 从提供给VCO的主环的可编程延迟单元的控制输入的集合可以向内部子环的可编程延迟单元提供不同的一组控制输入。 VCO的最小频率输出由主环路可编程延迟单元强度控制，VCO的最大频率输出由主环可编程延迟单元与内部子环可编程延迟单元的强度比控制。 通过修改内部子环和主环可编程延迟单元的控制输入，可以将最小和最大频率输出，从而将这两个频率输出之间的范围编程为可编程。

公开(公告)号：US20080272820A1

公开(公告)日：2008-11-06

申请号：US12132871

申请日：2008-06-04

申请人： David William Boerstler ,  Eskinder Hailu ,  Mack Wayne Riley ,  Michael Fan Wang

发明人： David William Boerstler ,  Eskinder Hailu ,  Mack Wayne Riley ,  Michael Fan Wang

IPC分类号： H03K3/00

CPC分类号： H03K23/662 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126

摘要： A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.

摘要翻译： 提供了一种方法，装置和计算机程序以减少模式转换期间的瞬态电流摆动。 传统上，芯片上的瞬态电源电压波动占大部分电源。 串联电感和电阻的数量通常最小化，同时在电源电压和地之间增加大的去耦电容。 然而，不能实现串联电感和电阻的降低的情况。 因此，为了帮助控制瞬态电流摆动，以受控的方式执行时钟频率的降低。

公开(公告)号：US20080229270A1

公开(公告)日：2008-09-18

申请号：US12128754

申请日：2008-05-29

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G06F17/50 ,  H03K3/017

CPC分类号： H03K5/1565 ,  H03K2005/00058 ,  H03K2005/00221

摘要： A design structure for a Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.

摘要翻译： 提供了一种用于占空比校正（DCC）电路的设计结构，其中已知DCC电路拓扑中的场效应晶体管（FET）中的对被替换为与DCC电路的开关耦合的线性电阻器，使得当开关断开时， 输入信号通过线性电阻器路由。 线性电阻器比FET更容忍工艺，电压和温度（PVT）波动，因此，所得到的DCC电路与使用FET的已知DCC电路拓扑结构相比，具有PVT波动的DCC校正范围相对较小的变化。 线性电阻器可以与开关并联设置并且与具有相对较大电阻值的一对FET串联。 线性电阻器提供上拉或下拉输入信号的脉冲宽度的电阻，以便对输入信号的占空比提供校正。

公开(公告)号：US20080222585A1

公开(公告)日：2008-09-11

申请号：US12126076

申请日：2008-05-23

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

IPC分类号： G06F17/50

CPC分类号： H03L7/0995 ,  H03K3/0315 ,  H03K5/133

摘要： A design structure embodied in a machine readable medium used in a design process includes an interleaved voltage-controlled oscillator, including a ring circuit of main logic inverter gates; a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates; wherein each delay element comprises a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages; and a proportional section for regulating signal transmission through at least one logic inverter gate; at least one temperature compensation circuit responsive to a compensating voltage input that is proportional to temperature; an electronic circuit in communication with the temperature compensation circuit and configured to provide a voltage signal responsive to temperature; an amplifier in connection with the electronic circuit to amplify the voltage signal; and a DC offset generator configured to adjust the voltage of the amplified voltage signal.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括交错压控振荡器，包括主逻辑逆变器门的环形电路; 多个延迟元件，与所述主逻辑反相器门的选定序列并联连接; 其中每个延迟元件包括前馈部分，其包括用于响应于一个或多个控制电压来调节通过前馈元件的信号传输的控制; 以及用于调节通过至少一个逻辑反相器门的信号传输的比例部分; 响应于与温度成比例的补偿电压输入的至少一个温度补偿电路; 与所述温度补偿电路通信并且被配置为提供响应于温度的电压信号的电子电路; 与电子电路相连的放大器，用于放大电压信号; 以及配置成调整放大的电压信号的电压的DC偏移发生器。

公开(公告)号：US07417480B2

公开(公告)日：2008-08-26

申请号：US11457637

申请日：2006-07-14

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.

摘要翻译： 提供了一种占空比校正（DCC）电路，其中已知DCC电路拓扑中的成对的场效应晶体管（FET）被连接到DCC电路的开关的线性电阻器代替，使得当开关断开时，输入信号被路由 通过线性电阻。 线性电阻器比FET更容忍工艺，电压和温度（PVT）波动，因此，所得到的DCC电路与使用FET的已知DCC电路拓扑结构相比，具有PVT波动的DCC校正范围相对较小的变化。 线性电阻器可以与开关并联设置并且与具有相对较大电阻值的一对FET串联。 线性电阻器提供上拉或下拉输入信号的脉冲宽度的电阻，以便对输入信号的占空比提供校正。

公开(公告)号：US07392419B2

公开(公告)日：2008-06-24

申请号：US11171756

申请日：2005-06-30

申请人： David William Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki ,  Jieming Qi

发明人： David William Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki ,  Jieming Qi

IPC分类号： G06F1/04

CPC分类号： H03K19/017581 ,  H03K19/00323 ,  H03K19/00346

摘要： The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.

摘要翻译： 本发明提供了一种系统，包括电平移位器，其被配置为从第一功率域接收第一时钟信号，以接收计数器信号，以响应于所接收的计数器信号选择多个中间电压中的一个，并且产生 响应于所接收的第一时钟信号和所选择的中间电压的第二时钟信号。 计数器耦合到电平移位器并被配置为接收分频时钟信号和比较结果信号，并且响应于接收到的分频时钟信号和比较结果信号产生计数器信号。 分频器耦合到计数器并且被配置为接收第一时钟信号并响应于接收到的第一时钟信号产生分频时钟信号。 滤波器耦合到电平移位器并且被配置为接收第二时钟信号并响应于所接收的第二时钟信号产生第一比较信号。 固定电位被配置为产生第二比较信号。 比较器耦合到滤波器，固定电位和计数器，并且被配置为接收第一比较信号和第二比较信号，并且响应于接收的第一比较信号和第二比较信号产生比较结果信号。

公开(公告)号：US07391277B2

公开(公告)日：2008-06-24

申请号：US11458753

申请日：2006-07-20

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

IPC分类号： H03B27/00

CPC分类号： H03L7/0995 ,  H03K3/0315 ,  H03K5/133

摘要： An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.

摘要翻译： 公开了一种交错压控振荡器（VCO）。 VCO包括环形电路，其包括主逻辑反相器门的串联连接，与主逻辑反相器门的选定序列并联连接的多个延迟元件，至少一个温度补偿电路，包括与 一个或多个场效应晶体管，所述场效应晶体管响应于与温度成比例的补偿电压输入;以及电子电路，其与所述至少一个温度补偿电路进行信号通信，并且被配置为提供响应于温度的电压信号。 每个延迟元件包括前馈部分，其包括用于响应于一个或多个控制电压来调节通过前馈元件的信号传输的控制，以及比例部分，包括用于调节通过至少一个逻辑反相器门的信号传输的控制。

公开(公告)号：US20080143419A1

公开(公告)日：2008-06-19

申请号：US12036936

申请日：2008-02-25

申请人： David William Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki ,  Jieming Qi

发明人： David William Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki ,  Jieming Qi

IPC分类号： H03L5/00

CPC分类号： H03K19/017581 ,  H03K19/00323 ,  H03K19/00346

摘要： The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.

摘要翻译： 本发明提供了一种系统，包括电平移位器，其被配置为从第一功率域接收第一时钟信号，以接收计数器信号，以响应于所接收的计数器信号选择多个中间电压中的一个，并且产生 响应于所接收的第一时钟信号和所选择的中间电压的第二时钟信号。 计数器耦合到电平移位器并被配置为接收分频时钟信号和比较结果信号，并且响应于接收到的分频时钟信号和比较结果信号产生计数器信号。 分频器耦合到计数器并且被配置为接收第一时钟信号并响应于接收到的第一时钟信号产生分频时钟信号。 滤波器耦合到电平移位器并且被配置为接收第二时钟信号并响应于所接收的第二时钟信号产生第一比较信号。 固定电位被配置为产生第二比较信号。 比较器耦合到滤波器，固定电位和计数器，并且被配置为接收第一比较信号和第二比较信号，并且响应于接收的第一比较信号和第二比较信号产生比较结果信号。

公开(公告)号：US07363178B2

公开(公告)日：2008-04-22

申请号：US11555018

申请日：2006-10-31

申请人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Bin Wan

发明人： David William Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Bin Wan

IPC分类号： G01R29/02

CPC分类号： G01R31/31922 ,  G01R29/0273 ,  G01R31/31725 ,  G01R31/31727

摘要： In one embodiment, the disclosed methodology and apparatus measure relative duty cycle information of a clock signal with respect to an input node as the clock signal travels to selected nodes of a clock distribution network on an electronic circuit. The apparatus operates in a benchmark mode to determine benchmark duty cycle information and then subsequently operates an a relative mode to determine relative duty cycle information of the clock signal at a selected node in comparison to the clock signal at an external input node.

摘要翻译： 在一个实施例中，当时钟信号传播到电子电路上的时钟分配网络的选定节点时，所公开的方法和装置测量相对于输入节点的时钟信号的相对占空比信息。 该装置在基准模式下操作以确定基准占空比信息，然后随后操作相对模式，以确定与外部输入节点处的时钟信号相比在所选节点处的时钟信号的相对占空比信息。

公开(公告)号：US07360135B2

公开(公告)日：2008-04-15

申请号：US11848314

申请日：2007-08-31

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi

IPC分类号： G01R31/28 ,  H03K3/017

CPC分类号： H03K5/1565 ,  G01R31/31727 ,  G01R31/3187

摘要： An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance. A chip level built-in circuit automatically calibrates the duty cycle correction (DCC) circuit setting for each chip. The chip level built-in circuit includes a clock generation macro unit, a simple duty cycle correction (DCC) circuit, an array slice and built-in self test unit, and a DCC circuit controller. A built-in self test provides results, i.e. pass or fail, of an array to the DCC circuit controller. If the result of the built-in self test is a pass, then the current DCC circuit controller's DCC control bit setting is set as the setting for the chip. If the result from the built-in self test is a fail, the DCC circuit controller's DCC control bits setting is incremented to a next setting and the self-test is performed again.

摘要翻译： 一种用于自动校准占空比电路以实现最大性能的装置和方法。 芯片级内置电路自动校准每个芯片的占空比校正（DCC）电路设置。 芯片级内置电路包括时钟生成宏单元，简单占空比校正（DCC）电路，阵列片和内置自检单元以及DCC电路控制器。 内置的自检向DCC电路控制器提供阵列的结果，即通过或失败。 如果内置自检的结果是通过，则将当前DCC电路控制器的DCC控制位设置设置为芯片的设置。 如果内置自检的结果为失败，DCC电路控制器的DCC控制位设置将增加到下一个设置，并再次执行自检。